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fedl7406-02 issue date:july 9, 2013 ML7406 868mhz srd rf transceiver ic 1 / 104 overview ML7406 is a low power consumption sub ghz rf transceiver, which includes rf, if, modem, baseband processor, host interface. ML7406 can be used for mainly ism(industrial, scientific and medical) or srd(short range device). (en13757-4:2011: wireless m-bus) packet format can be processed by on-chip hardware. ML7406 and ml7344 have the same package, pins assignment and major registers. 1 10 100 1000 frequency [mh ] 250 500 750 0 ML7406 series rf: 750mhz to 960mhz rate: 1.2kbps to 500kbps (fsk/gfsk) channel spacing: 100 khz to 1.6mhz wireless m-bus ieee802.15.4g (fec not supported) arib std-t108 1000 ml7344 series rf: 160mhz to 510mhz rate: 1.2kbps to 15kbps (fsk/gfsk) channel spacing: 25 khz wireless m-bus arib std-t67 ML7406 series ml7344 series data rate [kbps] (32pin wqfn) a rib std t67 (426/429 mhz) wireless m-bus (868mhz) wireless m-bus (169mhz) ieee802.15.4g (780 to 950mhz)
fedl7406-02 ML7406 2/104 features ? supported standard ? etsi en 300 220 (europe) ? en 13757-4:2011 (wireless m-bus) ? ieee802.15.4g ? arib std t108 (japan) ? rf frequency: 750mhz to 960mhz ? realized high resolution modulation by using fractional n type pll direct gfsk modulation ? modulation: gfsk/gmsk/fsk/msk (msk is a case that fsk modulation index = 0.5) ? data transmission rate: 1.2 to 500 kbps ? data encoding/decoding by hw: nrz, manchester, 3 out of 6 ? data whitening by hw ? programmable frequency channel filters ? programmable frequency deviation function ? tx/rx data inverse function ? 26 mhz oscillator circuits version (ML7406c) ? tcxo (26 mhz) direct input version (ML7406t) ? spxo input(cmos level) version (ML7406s) ? oscillator capacitance fine tuning function ? on chip low speed rc oscillation circuit ? low speed clock adjustment function ? frequency fine tuning function (using fractional n type pll) ? synchronous serial peripheral interface(spi) ? on-chip tx pa. (20 mw / 10 mw / 1 mw selectable) ? tx power fine tuning function (0.2 db) ? tx power automatic ramping control ? external tx pa control function ? rssi indicator and threshold judgment function ? high speed carrier checking function ? afc function (if frequency automatic adjustment by fractional n type pll adjustment) ? antenna diversity function ? automatic wake up, auto sleep function (external rtc input or internal rc oscillator selectable) ? general purpose timer (2ch) ? test pattern generator (pn9 ,cw, 01 pattern , all?1?, all?0? output ) ? packet mode function ? wireless m-bus packet format (format a/b) ? general purpose packet format (format c) ? max.255 byte (format a/b), 204t byte (format c) ? tx fifo (64 byte), rx fifo (64 byte) ? rx preamble pattern detection (max.4 byte) ? automatic tx preamble length generation (max.length 16383 byte) ? syncword setting function (max. 4byte 2 type) ? program crc function (crc32/crc16/crc8 selectable, fully programmable polynomial) ? wireless m-bus field checking function (c-field/m-field/a-field can be detected automatically) (note) proprietary packet fo rmat is possible depending on setting ? supply voltage 1.8 v to 3.6 v (tx power 1 mw mode) 2.3 v to 3.6 v (tx power 10 mw mode) 2.6 v to 3.6 v (tx power 20 mw mode) ? operational temperature -40 ? c to 85 ? c
fedl7406-02 ML7406 3/104 ? current consumption (868 mhz) deep sleep mode 0.1 a (typ.) sleep mode2 0.56 a (typ.) (retains registers, fifo) idle mode 1.4 ma (typ.) tx 20 mw 34 ma (typ.) 10 mw 24 ma (typ.) 1 mw 13 ma (typ.) rx 15 ma (typ.) (@100kbps) ? package 32pins wqfn (5mm 5mm) p-wqfn32-0505-0.50 lead free, rohs compliance
fedl7406-02 ML7406 4/104 product name description convention 1) numbers description ?0xnn? indicates hexa decimal. ?0bnn? indicates binary. example: 0x11= 17(decimal), 0b11= 3(decimal) 2) registers description [: b ] register example: [rf_status: b0 0x0b] register register name: rf_status bank no: 0 register address: 0x0b 3) bir name description ([: b ()]) example: set_trx[3:0] ([rf_status: b0 0x0b(3-0)]) bit name: set_trx register name: rf_status bank no: 0 register address: 0x0b bit location: bit3 to bit0 4) in this document ?tx? stands for transmittion. ?rx? stands for reception. ML7406 y gdz05bl y = c: crystal input s: spxo input t: tcxo input
fedl7406-02 ML7406 5/104 block diagram lna mix bpf limiter pa lo pll vco rf l c ML7406 s p i phy rssi fifo reg_out reg_core xin xout i r c bb sclk sdo sdi scen gpio0 vbg resetn a_mon lna_p pa_out reg(pa) reg reg_pa regpdin vb_ext lp ind1,2 ed_val demod rf_manager digital mod fmap wakeup timer gpio1/2/3 general timer1/2 ext_clk 20mw/ 1mw rc osc temp clk cal 26mhz xtal osc
fedl7406-02 ML7406 6/104 pin configuration 32 pin wqfn lna_p a_mon vdd_pa reg_pa pa_out gpio3 gpio2 gpio1 24 23 22 21 20 19 18 17 vdd_rf 25 16 gpio0 lp 26 15 sdi vdd_cp 27 14 scen ind1 28 13 sclk gnd_vco 29 12 sdo ind2 30 11 regpdin vb_ext 31 10 ext_clk vdd_vco 32 9 vddio 12345678 vdd_reg vbg reg_out reg_core xin (n.c.) xout (tcxo, spxo) n.c. resetn Ypkg gnd (t.b.d.) gnd pad note: gnd pad in the middle of the lsi is reverse side (name:reversed side gnd)
fedl7406-02 ML7406 7/104 pin definitions symbols i : digital input o : digital output is : shmidt trigger input io : digital input/output i a : analog input o a : analog output 1 o ah : analog output 2 io a : analog input/output o rf : rf output v ddio : i/o power supply v ddrf : rf power supply gnd : ground rf and analog pins pin pin name reset state i/o active level function 20 pa_out ? o rf ? rf antenna output 23 a_mon ? o a ? temperature information output (*1) 24 lna_p ? i a ? rf antenna input 26 lp ? io a ? pin for loop filter 28 ind1 ? io a ? pin for vco tankl inductor 30 ind2 ? io a ? pin for vco tank inductor 31 vb_ext ? io a ? pin for smothing capacitor for internal bias *1 this pin can be configured by [mon_ctrl:b0 0x4d] register, no signal assigned as default setting. spi interface pins pin pin name reset state i/o active level function 12 sdo o/l o h or l spi data output or dclk (*1) 13 sclk i is p or n spi clock input 14 scen i is l spi chip enable l: enable h: disable 15 sdi i is h or l spi data input or dio (*1) *1 please refer to ?dio function?
fedl7406-02 ML7406 8/104 regulator pins pin pin name reset state i/o active level function 2 vbg (*1) ? o ah ? pin for decouppling capacitor 3 reg_out (*1) ? o ah ? requlator1 ouput (typ. 1.5v) 4 reg_core ? o a ? requlator2 ouput (typ. 1.5v) 11 regpdin i i h power down control pin for regulator fix to ?l? for nomal use. ?h? is for deep sleep mode. 21 reg_pa (*1) ? o ah ? regulator output for pa block *1 these pin will output 0v in the sleep state. miscellaneous pin pin name reset state i/o active level function 5 xin n.c.(*2) i ? i a ? p or n ? 26mhz crystal pin1 (note) in case of tcxo or spxo, it must be open. 6 xout tcxo(*2) spxo(*2) o o a i a i p or n 26mhz crystal pin 2 or tcxo input, spxo input 8 resetn i i s l reset l: hardware reset enable (forcing reset state) h: normal operation 10 ext_clk i io p or n digital i/o (*3) reset state: external rtc (32khz) input. 16 gpio0 o/h io or od(*1) h or l digital gpio (*4) reset state: interrupt indication signal output 17 gpio1 o/l io or od(*1) h or l digital gpio (*5) reset state: clock output 18 ant_sw/ gpio2 o/l io or od(*1) h or l digital gpio (*6) reset state: antenna diversity selection control signal 19 trx_sw/ gpio3 o/l io or od(*1) h or l digital gpio (*7) reset state: tx ?rx selection signal control (note) *1 od is open drain output. *2 the following pin names are different depend on products. pin no. ML7406c ML7406s ML7406t 5 xin n.c. n.c. 6 xout spxo tcxo (note) in case of using tcxo/spxo, set tcxo_en or spxo_en =0b1. please make sure only one of the register tcxo_en, spxo_en, xtal_en_en is set to 0b1. *3 please refer to [extclk_ctr: b0 0x52] register. *4 please refer to [gpio0_ctrl: b0 0x4e] register
fedl7406-02 ML7406 9/104 *5 please refer to [gpio1_ctrl: b0 0x4f] register *6 please refer to [gpio2_ctrl: b0 0x50] register *7 please refer to [gpio3_ctrl: b0 0x51] register power supply/gnd pins pin pin name reset state i/o active level function 1 vdd_reg ? v ddio ? power supply pin for regulator (input voltage: 1.8v to 3.3v) 9 vddio ? v ddio ? power supply for digital i/o (input voltage: 1.8 to 3.6v) 22 vdd_pa ? v ddio ? power supply for pa block (input voltage: 18 to 3.6v, depending on tx mode) 25 vdd_rf ? v ddrf ? power supply for rf blocks (reg-out is connected, typ.1.5v) 27 vdd_cp ? v ddrf ? power supply for charge pump (reg-out is connected, typ.1.5v) 32 vdd_vco ? v ddrf ? power supply for vco (reg_out is connected, typ.1.5v) 29 gnd_vco ? gnd ? gnd for vco unused pins treatment unused pins treatments are as follows: unused pins treatment pin name pins number recommended treatment n.c. 5 open n.c. 7 gnd or open ext_clk 10 gnd a_mon 23 gnd gpio0 16 open gpio1 17 open gpio2 18 open gpio3 19 open (note) *1 if input pins are high-impedence state and leave open, exces s current could be drawn. care must be taken that unused input pins and unused i/o pins should not be left open. *2 upon reset, gpio1 pin is clk_out function. if this function is not used, the clock must to be disabled by setting 0b000 to gpio1_io_cfg[2:0] ([gpio1_ctrl: b0 0x4f (2-0)]). if this pin is left open while outputing clock signal, it may affect rx sensitivity.
fedl7406-02 ML7406 10/104 electrical characteristics absolute maximum rating ta=-40 ? c to +85 ? c and gnd=0v is the typical conditoin if not defined specific condition. item symbol condition rating unit i/o power supply v ddio -0.3 to +4.6 v rf power supply v ddrf -0.3 to +2.0 v rf input power p rfi antenna input in rx 0 dbm rf output voltage v rfo pa_out(#20) -0.3 to +4.6 v voltage on analog pins 1 v a -0.3 to +2.0 v voltage on analog pins 2 v ah -1.0 to +4.6 v voltage on digital pins v d -0.3 to +4.6 v digital input current idi -10 to +10 ma digital output current ido -8 to +8 ma power dissipation pd ta= +25 ? c 1.2 w strage temperature tstg ? -55 to +150 ? c
fedl7406-02 ML7406 11/104 recommended operation conditions item symbol condition min typ max unit power supply (i/o) v ddio vddio pin and vdd_reg pin (*1) 1.8 3.3 3.6 v vdd_pa pin tx power 1mw mode 1.8 3.3 3.6 v vdd_pa pin tx power 10mw mode 2.3 3.3 3.6 v power supply (pa) v ddpa vdd_pa pin tx power 20mw mode 2.6 3.3 3.6 v operational temperature ta ? -40 +25 +85 ? c digital input rising time t ir digital input pins (*1) ? ? 20 ns digital inputfalling time t if digital input pins (*1) ? ? 20 ns digital output output load c dl all digital output pins ? ? 20 pf master clock frequency (xin,xout,tcxo,spxo pins) f mck1 ? (*2) 26 (*2) mhz master clock accuracy (*2) a cmck1 ? -85 ? +85 ppm tcxo input voltage v tcxo dc cutoff tcxo optionis selected 0.8 ? 1.5 vpp spi clock inputfrequency f sclk sclk pin 0.032 2 16 mhz spi clock input duty cycle ratio d sclk sclk pin 45 50 55 % rf frequency f rf 750 ? 960 mhz *1 in the pin description, i or is are specified as the i/o. *2 indicating frequency deviation during tx-rx operation. in order to support various standards, please apply the frequency accuracy for each standard to meet the requirements. specification required accuracy wireless m-bus s mode 60 ppm(meter) 25 ppm(other) wireless m-bus t mode 60 ppm(meter) 25 ppm(other) wireless m-bus c mode 25 ppm arib std-t108 20 ppm
fedl7406-02 ML7406 12/104 (note) below values are not taking individual lsi variations into consideration. power consumption item synbol condition min typ (*2) max (*5) unit power consumption (*1) i dd_dslp deep sleep mode (not retaining registers, all function halt) ? 0.1 9 (0.8) a i dd_slp2 sleep mode 2 (*3) ? 0.56 20 (3.2) a i dd_slp3 sleep mode 3 (*3) ? 0.7 20.2 (3.2) a i dd_slp4 sleep mode 4 (*3) ? 2.5 22 (5.1) a i dd_idle idle state ? 1.4 ? ma i dd_rx rf rx state (*4) ? 15 ? ma i dd_tx1 rf tx state (1mw)(*4) ? 13 ? ma i dd_tx10 rf tx state (10mw) (*4) ? 24 ? ma i dd_tx20 rf tx state (20mw) (*4) ? 34 ? ma *1 power consumption is sum of current consumption of all power supply pins. *2 ?typ? value is centre value under condition of vddio=3.3v, 25 ? c. *3 the definition od each sleep stae is shown in following table. state. register fifo rc osc. (32khz) low clock timer sleep mode 1 ML7406 does not support sleep mode 1 sleep mode 2 retain retain off - sleep mode 3 retain retain external input on sleep mode 4 retain retain on on *4 current consumption when rf frequency is 868mhz. *5 () means maximum value (reference value) under condition of 25 ? c. (note) it is inhibited the trnasiton from sleep modes to deep sleep mode in one power supply cycle.
fedl7406-02 ML7406 13/104 dc characteristics item symbol condition min typ max unit v ih1 digital input pin vddio 0.75 ? vddio v voltage input high v ih2 xin pin 1.35 ? 1.5 v v il1 digital input pin 0 ? vddio 0.18 v voltage input low v il2 xin pin 0 ? 0.15 v resetn pin sdi, sclk, scen pins schmittriggerthreshold high level v t+ ext_clk pin ? 1.2 vddio 0.75 v resetn pin sdi, sclk, scen pins schmittriggerthreshold low level v t- ext_clk pin vddio 0.18 0.8 ? v i ih1 digital input pins -1 ? 1 a i ih2 xin pin -0.3 ? 0.3 a i il1 digital input pins -1 ? 1 a input leakage current i il2 xin pin -0.3 ? 0.3 a i ozh digital input pins -1 ? 1 a tri-state output current leakage i ozl digital input pins -1 ? 1 a voltage output level h v oh ioh=-4ma vddio 0.8 ? vddio v voltage output level l v ol iol=4ma 0 ? 0.3 v reg main reg_core pin, reg_out pin, applicable to all states except sleep state 1.4 1.5 1.6 v regulator output voltage reg sub reg_core pin sleep state 0.95 1.3 1.65 v c in input pins ? 6 ? pf c out output pins ? 9 ? pf c rfio rf inout pins ? 9 ? pf pin capacitance c ai analog input pins ? 9 ? pf
fedl7406-02 ML7406 14/104 rf characteristics modulated data rate : 1.2kbps to 500kbps modulation fomats : 2gfsk/2fsk channel spacing : 60khz to 1.6mhz the measurement point is at antenna end specified in the recommended circuits. [rf frequency] item condition min typ max unit rf frequency lna_p, pa_out pins 750 ? 960 mhz (note) 1)frequency range can be adjusted from 750mhz to 960mhz by changing external components parameters. 2)if channel frequency is similar frequency range of integral multiple of the master clock, it may not be able to use this mode. please refer to the ?channel frequency setting? section for detail. [tx characteristics] item condition min typ max unit 20mw(13dbm) mode 9 13 15 dbm 10mw(10dbm) mode 6 10 12 dbm tx power 1mw(0dbm) mode -4 0 4 dbm frequency deviation fine tuning range [fdev] (*1) 0.025 ? 400 khz the sencod order harmonic ? -35 -30 dbm spurious emission level(10mw mode) the third order harmonic ? -35 -30 dbm *1. depending on the frequency, max.frequency may be changed. [rx characteristics] item condition min typ max unit 32.768kbps mode ? -108 ? dbm minimum rx sensitity ber<0.1% 100kbps mode ? -106 -100 dbm maximum rx input level ber<0.1% 0 ? ? dbm minimum energy detection level (ed value) ? -107 -100 dbm energy detection range dynamic range 60 70 ? db energy detection accuracy -6 ? +6 db local frequency ? -63 -57 dbm secondary emission level frequency over 1000mhz ? -57 -47 dbm
fedl7406-02 ML7406 15/104 rc oscillation circuits characteristics ML7406 has on-chip low speed rc clock generator. for details, please refer to ?lsi state transition control/sleep setting? section. item symbol condition min typ max unit rcosc oscillation frequency f rcosc ? 44 ? khz :w spi interface characteristics item symbol condition min typ max unit sclk clock frequency f sclk 0.032 2 16 mhz scen input setup time t scensu 30 ? ? ns scen input hold time t scenh 30 ? ? ns sclk high pulse width t sclkh 28 ? ? ns sclk low pulse width t sclkl 28 ? ? ns sdi input setup time t sdisu 5 ? ? ns sdi input hold time t sdih 15 ? ? ns scen invert period t scenni 200 ? ? ns sdo output delay time t sdodly load capacitance cl=20pf ? ? 22 ns (note) all measurement condition for the timings are v ddio * 20% level and v ddio * 80% level. scen sclk sdo sdi msb in bits6-1 lsb in f sclk t sclkh t sdisu t sclkl msb out bits6-1 lsb out t scenh t sdodly t sdih t scensu scen t scenni
fedl7406-02 ML7406 16/104 dio iinterface characteristics item symbol condition min typ max unit dio input setup time t disu 1 ? ? sec dio input hold time t dih 0 ? ? ns dio output hold time t doh 20 ? ? ns dclk frequency accuracy (*1) (tx) f dclk_tx -clock frequency deviation ? +clock frequency deviation khz dclk frequency accuracy (*2) (rx) f dclk_rx -30 ? +30 % dclk output duty cycle (tx) d dclk_tx 45 ? 55 % dclkoutput duty cycle (rx) d dclk_rx load capacitance cl=20pf 30 ? 70 % *1 if there is no decimal point generated in the tx data rate setting caluclation, (see [tx_rate_h: b1 0x02]), master clock frequency deviation is max.and min.of tx dclk frequency. *2 max.and min.of rx dclk frequency indicates jitter of recovered clock from rx signal upon synchronization. (note) all timing measurement conditions are v ddio * 20% and v ddio * 80%. dclk dio(input) valid valid f dclk_tx / f dclk_rx t disu t dih dio(output) valid valid valid t doh valid
fedl7406-02 ML7406 17/104 power-on characteristics item symbol condition min typ max unit power-on stable time t pwon power on state (all power pins) ? ? 5 ms (note) all timing measurement conditions are v ddio * 20% and v ddio * 80%. reset characteristics item symbol condition min typ max unit resetn release delay time (power on period) t rdl1 all power pins after power on 150 ? ? ms resetn pulse period (start-up from vddio=0v) t rpw1 200 ? ? ns resetn pulse period 2(*1) (start-up from vddio 0v) t rpw2 after vddio>1.8v 150 ? ? ms resetn input delay time t rdl2 1 ? ? s resetn rising edge delay time t rrst ? ? 1 ms (note) all timing measurement conditions are v ddio * 20% level and v ddio * 80% level. (*1) when starting from vddio 0v, a pulse must be sent to vresetn after ddio exceeds 1.8v. vddio vdd level gndlevel resetn t rdl1 t rpw1 t rpw2 1.8v t rdl2 below 1.8v t rrst vdd vdd level gnd level t pwon 80% 20%
fedl7406-02 ML7406 18/104 deep sleep mode characteristics item symbol condition min typ max unit regpdin rising edge delay time t rpfd vddio=?h? 0 ? ? s regpdin assert time t rppls vddio=?h? 1.2 ? ? ms regpdin release delay time t rprd vddio=?h? 1.5 ? ? ms (note) all timing measurement conditions are v ddio 20% and v ddio 80%. clock output characteristics ML7406 has clock output function. clock output can be controlled by dmon_set([mon_ctrl: b0 0x4d(3-0)]) and [gpion_ctrl: b0 0x4e-0x51] registers (n=0 to 3). upon reset, clock is output through gpio1 pin. item symbol condition min typ max unit clock output frequency f clkout 0.0064 3.33 26 mhz 8.66mhz 33 ? 67 % clock output duty cycle (*1) d clkout load capacitance cl=20pf all conditions except above 48 50 52 % *1 duty cycle is high:low = 1:2 , only when 8.66mhz is used. please refer to [clk_out: b1 0x01] register. (note) all timing measurement conditions are v ddio 20% and v ddio 80%. vddio vdd level gnd level resetn t rpfd regpdin t rprd t rppls gpio* f clkout
fedl7406-02 ML7406 19/104 functional description host interface serial peripheral interface (spi) ML7406 has a spi, which supports slave mode. host mcu can read/write to the ML7406 registers and on-chip fifo using mcu clock. single access mode and burst access mode are also supported. [single access mode timing chart] in write operation, data will be stored into internal register at rising edge of clock which is capturing d0 dat. during write operation, if setting scen line to ?h?, the data will not be stored into register. for more details of scen invert perios, plea se refer to the ?spi interface characteristics?. after the internal clock is stabilized, the data will be written into the registe r in synchronization with the internal clcok. scen sdi sclk write data field address field w scen sdi sclk address field r sdo data read field [write] [read] a 6 a 0 a 6 a 0 d 7 d 0 d 7 d 0 (register write timing) before clock stable after clock stable d7-0 d7-0 ?1? ?0? up to 0.45 s
fedl7406-02 ML7406 20/104 [burst access mode timing chart] by maintaining scen line as ?l?, burst access mode will be active. by setting scen line to ?h?, exiting from the burst access mode. during burst access mode, address will be automatically incremented. when scen line becomes ?h? before clock for d0 is input, data transaction will be aborted. (note) if destination is [wr_tx_fifo: b0 0x7c], [rd_fifo: b0 0x7f], address will not be incremented. and continuous fifo access is possible. [write] read data field scen write data field address field w scen address field r write data field read data field [read] a 6 a 0 a 6 a 0 d 7 d 0 d 7 d 0 sdo sdi sclk (register write timing) before clock stable after clock stable d7-0 d7-0 d7-0 d7-0 ?1? ?0? up to 0.45 s up to 0.45 s sclk sdi
fedl7406-02 ML7406 21/104 lsi state transition control lsi state transition instruction state can be controlled from mcu by setting registers below. state transition command instruction tx_on set_trx ([rf_status: b0 0x0b(3-0)]) = 0b1001 rx_on set_trx ([rf_status: b0 0x0b(3-0)]) = 0b0110 trx_off set_trx ([rf_status: b0 0x0b(3-0)]) = 0b1000 force_trx_off set_trx ([rf_status: b0 0x0b(3-0)]) = 0b0011 sleep sleep_en([sleep/wu_set: b0 0x2d(0)]) = 0b1 vco_cal vco_ca_lstart([vco_cal_start: b0 0x6f(0)])= 0b1 state can be changed without command from mcu. if one of the following condition is met, state is changed automatically according to the following table. in order to enable thes e functions, the following registers must be programmed. function control bit name automatic txon after fifo write completion (auto_tx) auto_tx_en([rf_status_ctrl: b0 0x0a(4)]) automatic txon during fifo wrtie (fast_tx) fast_tx_en([rf_status_ctrl: b0 0x0a(5)]) rf state setting after packet transmission completion txdone_mode([rf_status_ctrl: b0 0x0a(1-0)]) rf state setting after packet reception completion rxdone_mode([rf_status_ctrl: b0 0x0a(3-2)]) automatic rx_on/tx_on by wake-up time wakeup_mode([sleep/wu_set:b0 0x2d(6)]) wakeup_en([sleep/wu_set:b0 0x2d(4)]) automatic vco calibration after exit from sleep auto_vcocal_en([vco_cal_start: b0 0x6f(4)]) automatic sleep by timer wu_duration_en([sleep/wu_set: b0 0x2d(5)]) automatic sleep by high speed carrier checking mode fast_det_mode_en([cca_ctrl:b0 0x39(3)]) force_trx_off after pll unlock detection during tx pll_ld_en([pll_lock_detect: b1 0x0b(7)])
fedl7406-02 ML7406 22/104 state diagram each state transition control is decr ibed in the follwing state diagram. lsi state diagram (note) the following state transition is inhibited; deep sleep any state sleep tx_on trx_off force_trx_off sleep tx completion (trx_off) tx start trx_off force_trx_off sleep rx_on v co_cal completion start v co_cal rx completion ( trx_off) rx start (syncword detection) rx_on tx_on rx_on start vco_cal trx_off force_trx_off vco_cal completion sleep exit from sleep sleep exit from deep sleep deep sleep [state] deep sleep : deep sleep sleep : sleep trx_off/idle : idle (tx-rx stand-by) pll_wait : pll stand-by tx_on : tx ready (tx data waiting) transmit : tx on-going rx_on : rx stand-by (rx data waiting) receive : rx on-going vco_cal : vco calibration normal sequence (state transition) command from higher layer state ML7406 self controlled state transition state transition instruction pins control trasmit receive rx_on trx_off force_trx_off sleep tx_on pllwait trx_off force_trx_off sleep rx_on tx_on force_trx_off sleep trx_off force_trx_off sleep rx_on force_trx_off sleep trx_off force_trx_off sleep v cocal sleep exit from sleep trx_off idle deep sleep exit from deep sleep tx_on rx_on vco_cal sleep
fedl7406-02 ML7406 23/104 sleep setting deep_sleep mode: powers for all bloc ks except io pins are turned off. sleep mode: main regulator and 26mhz oscillation circuits are tured off. but sub-regulator is turned-on. the following registers can be programmed to control sleep state. function control bit name power control pdn_en([sleep/wu_set: b0 0x2d(1)]) wake-up setting wakeup_en([sleep/wu_set: b0 0x2d(4)]) wake-up timer clock source setting wut_clk_source([sleep/wu_set: b0 0x2d(2)]) internal rc oscillator control rc32k_en ([clk_set2: b0 0x03(3)]) setting method and internal state for deep_sleep and various sleep modes are as follows: sleep mode setting method main regulator sub regulator 26mhz oscillator rc oscilator low clock timer fifo deep_sleep resetn pin=?l? regpdin pin=?h? off off off off off off sleep1 not supported - - - - - - sleep2 [sleep/wu_set: b0 0x2d(4-0)] = 0b0_1001 (*2) [clk_set2: b0 0x03(3)] = 0b0 (default) off on off off(*1) off on sleep3 [sleep/wu_set: b0 0x2d(4-0)] = 0b1_1001 (*2) [clk_set2: b0 0x03(3)] = 0b0 (default) off on off off on on sleep4 [sleep/wu_set: b0 0x2d(4-0)] = 0b1_1101 (*2) [clk_set2: b0 0x03(3)] = 0b1 off on off on on on (*1) low speed clock is supplied from ext_clk pin. (*2) please set proper value to [sleep/wu_set: b0 0x2d(3)]. (note) contents of registers are not kept during deep_sleep. contents of registers are kept during sleep2,sleep3,sleep4.
fedl7406-02 ML7406 24/104 notes to set rf state ML7406 is able to change the internal rf state transition au tonomously (without commands from mcu) as well as rf state change commands from mcu. (please refer to ?lsi state transition instruction?). if both timing of operation (autonomous state and state change from mcu command) overlapped, unintentional rf state may occur. timing of autonomous state rf change is described in the following table. care must be taken not to overlap the conditions. function rf state change (before after) rf state transition timing (not from host mcu command) recommended process automatic tx after tx data transfer completion interrut occurs, { value [tx_rate_h/l: b1 0x02/03)] * 2 / 26}[ s] period. fast_tx mode trx_off/rx_on tx_on when fifo write access exceed trigger level +1, { value [rx_rate1_h/l:b1 0x04/05] * 5 / 26}[ s] period. tx_on trx_off tx_on rx_on rf state setting after tx completion tx_on sleep after tx completion interrupt (int[16] group3), { value [tx_rate_h/l:b1 0x02/03] * 2 / 26} [ s] period rx_on trx_off rx_on tx_on rf state setting after rx completion rx_on sleep after data rx completion interrupt (int[8] group2, { value [rx_rate1_h/l:b1 0x04/05] * 2 / 26}[ s] period sleep tx_on sleep rx_on after wake-up timer completion interrupt (int[6] group1), 1 clock cycle period defined by wut_clk_set[3:0] ([wut_clk_set:b0 0x2e (3-0)]). write access to [rf_status:b0 0x0b] is possible after rf state transition completion interrupt (int[3] group1), or move to the state defined by get_trx ([rf_status:b0 0x0b(7-4)]). sleep vco_cal tx_on wake-up timer sleep vco_cal rx_on after wake-up timer completion interrupt (int[6]: group1), before vco calibration completion interrupt (int[1] group1). write access to [rf_status:b0 0x0b] and bank2 is possible after vco calibration completion interrupt (iny[1] group1). tx_on sleep continuous operation timer rx_on sleep after continuous operation timer completion, 1 clock cycle period defined by wut_clk_set[3:0] ([wut_clk_set:b0 0x2e (3-0)]). high speed carrier checking rx_on sleep after cca completion interrupt, duration 6.3[ s]. write access to [rf_status:b0 0x0b] is possible after rf state transition completion interrupt (int[3] group1), or move to the state defined by get_trx ([rf_status:b0 0x0b(7-4)]). pll unlock detection tx_on trx_off after pll unlock detection interrupt (int[2] group1) occurs, duration 147[ s]. write access to [rf_status:b0 0x0b] is possible 147 s after pll unlock interrupt (int[2] group1) detected.
fedl7406-02 ML7406 25/104 packet handling function pack et format ML7406 supports wireless m-bus frame formata/b, and format c which is non wireless m-bus universal format. the following packet handling are supported in fifo mode or dio mode 1) preamble and syncword automatic insertion (tx) --- dio/fifo mode 2) preamble and syncword automatic detection (rx) --- dio/fifomode 3) preamble and syncword automatic deletion (rx) --- dio/fifo mode 4) crc data insertion (tx) --- fifo mode 5) crc check and error notification (rx) --- dio/fifo mode the following table shws control bits relative with the packet format function. function control bit name packet formatsetting pkt_format[1:0] ([pkt_ctrl1: b0 0x04(1-0)]) ieee 802.15.4g setting ieee802_15_4g_en ([pkt_ctrl1: b0 0x04(2)]) rx extended link layer mode disable rx_extpkt_off ([pkt_ctrl1: b0 0x04(3)]) data area bit order setting dat_lf_en ([pkt_ctrl1: b0 0x04(4)]) length area bit order setting len_lf_en ([pkt_ctrl1: b0 0x04(5)]) extended link layer mode setting ext_pkt_mode[1:0] ([pkt_ctrl1: b0 0x04(7-6)]) length field setting length_mode ([pkt_ctrl2: b0 0x05(0)]) (1) format a (wireless m-bus) by setting pkt_format[1:0] ([pkt_ctrl1: b0 0x04(1- 0)])=0b00, wireless m-bus format a is selected. format a consists of 1 st block, 2 nd block and optional block(s). each block has 2 bytes of crc. ?l-field? (1 st byte of 1 st block ) indicates packet length, which includes subsequenct user data bytes from ?c-field?. however, crc bytes and postamble are excluded. depending on ?l-field? value, 2 nd block and optional block(s) are added. the following [] indicates register address [bank #, address]. *1: each mode has different minimum value of n. *2: indicates tx fifo data storage area size. *3: indicates rx fifo data storage area size. *4: when rxdio_ctrl[1:0] ([dio_set: b0 0x0c(7-6)])=0b10, indicates dclk/dio output area. (*2) length msb lsb preamble sync word tx: automatic insertion rx: automatic detection, deletion l field manchester/3-out-of-6 applicable [b0 0x07(3-2,1-0)] 1st block 2nd block o p tional block postamble crc field c field m field a field ci field crc field data field crc field data field 1 byte 1 byte 2 bytes 6 bytes 2 bytes 1 byte 2 bytes 2 bytes max.15 bytes max.16 bytes 0/2-8 bits 10/18/ 32bits > n*2 (*1) bits crc applicable crc applicable crc applicable (*2) (*2) (*3) (*4) [b0 0x07] [b0 0x42] [b0 0x43] [b0 0x08] [b1 0x25-2e] [b0 0x05] [b0 0x7a/7b, 7d/7e] [b0 0x44]
fedl7406-02 ML7406 26/104 extended link layer format if ?ci-field? (1 st byte of 2 nd block)=0x8c or 0x8d, extended link layer is applied. the packet format is as follows: (a) ci-field = 0x8c for tx, if 2 bytes extention format is used, set ext_pkt_mode[1:0] ([pkt_ctrl1: b0 0x04(7-6)])=0b01. for rx, if rx_extpkt_off([pkt_ctrl1: b0 0x04(3)])=0b0, ML7406 recognizes ?ci-field? and rx operation is processed. *1: 1st block is identical to normal format a.. *2: indicates tx fifo data storage area size. *3: indicates rx fifo data storage area size. *4: when rxdio_ctrl[1:0] ([dio_set: b0 0x0c(7-6)])=0b10, indicating dclk/dio output area. length msb lsb preamble sync word l field manchester/3-out-of-6 applicable [b0 0x07(3-2,1-0)] 1st block (*1) 2nd block optional block postamble a cc field ci field cc field crc field data field crc field data field 1 byte 11 bytes 1 byte 1 byte 1 byte 1 byte 2 bytes 2 bytes max 12 bytes max 16 bytes 0/2-8 bits 10/18/ 32bits > n*2 bits crc applicable crc applicable c-crc field extended block (*2) (*2) (*3) (*4) [b0 0x07] [b0 0x42] [b0 0x43] [b0 0x44] [b0 0x08] [b1 0x25-2e] [b0 0x05] [b0 0x7a/7b, 7d/7e] ci field tx: automatic insertion rx: automatic detection, deletion
fedl7406-02 ML7406 27/104 (b) ci-field = 0x8d for tx, if 8 bytes extention format is used, set ext_pkt_mode[1:0] ([pkt_ctrl1: b0 0x04(7-6)])=0b10. for rx, if rx_extpkt_off([pkt_ctrl1: b0 0x04(3)])=0b0, ML7406 recognizes ?ci-field? and rx operation is processed. *1: 1 st block is identical to normal format a.. *2: indicating tx fifo data storage area size. *3: indicating rx fifo data storage area size. *4: when rxdio_ctrl[1:0] ([dio_set: b0 0x0c(7-6)])=0b10, indicating dclk/dio output area. length msb lsb preamble sync word l field manchester/3-out-of-6 applicable [b0 0x07(3-2,1-0)] 1st block (*1) 2nd block optional block postamble a cc field ci field cc field crc field data field crc field data field 1 byte 11 bytes 1 byte 1 byte 1 byte 1 byte 2 bytes 2 bytes max 15 bytes max 16 bytes 0/2-8 bits 10/18/ 32bits > n*2 bits crc applicable crc applicable c-crc field extended block sn field 4 bytes crc field 2 bytes crc a pp licable ci field (*2) (*2) (*3) (*2) (*4) [b0 0x07] [b0 0x42] [b0 0x43] [b0 0x44] [b0 0x08] [b1 0x25-2e] [b0 0x05] [b0 0x7a/7b, 7d/7e] tx: automatic insertion rx: automatic detection, deletion
fedl7406-02 ML7406 28/104 (2) format b (wireless m-bus) by setting pkt_format([pkt_ctrl1: b0 0x04(1-0)])=0b01, wireless m-bus format b is selected. format b consists of 1st block, 2nd block or optional block. each block after 2nd block has 2 bytes of crc. ?l-field? indicates packet length, which includes subsequent us er data bytes from ?c-field?. however, unlike format a, crc bytes are included (pastamble are exclueded). depending on ?l-field? value, 2nd block and optional block(s) are added. the following [] indicates register address [bank #, address]. *1: each mode has different minimum value of n. *2: indicates tx fifo data storage area size. *3: indicates rx fifo data storage area size. *4: when rxdio_ctrl[1:0] ([dio_set: b0 0x0c(7-6)])=0b10, indicating dclk/dio output area. length msb lsb preamble sync word l field manchester/3-out-of-6 applicable [b0 0x07(3-2,1-0)] 1st block 2nd block optional block postamble c field m field a field ci field crc field data field crc field data field 1 byte 1 byte 2 bytes 6 bytes 1 byte 2 bytes 2 bytes max 115 bytes max 126 bytes 0/2-8 bits 10/18/ 32bits > n*2 (*1) bits crc a pp licable crc applicable (*2) (*2) (*3) (*4) [b0 0x07] [b0 0x42] [b0 0x43] [b0 0x44] [b0 0x08] [b1 0x25-2e] [b0 0x05] [b0 0x7a/7b, 7d/7e] tx: automatic insertion rx: automatic detection, deletion
fedl7406-02 ML7406 29/104 extended link layer format if ?ci-field? (1 st byte of 2 nd block ) = 0x8c or 0x8d, extended link layer is applied. the packet format is as follows: (a) ci-field = 0x8c for tx, if 2bytes extention format is used, set ext_pkt_mode[1:0] ([pkt_ctrl1: b0 0x04(7-6)])=0b01. for rx, if rx_extpkt_off([pkt_ctrl1: b0 0x04(3)])=0b0, ML7406 recognizes ?ci-field? and rx operation is processed. *1: 1 st block is identical to normal format b.. *2: indicating tx fifo data storage area size. *3: indicating rx fifo data storage area size. *4: when rxdio_ctrl[1:0] ([dio_set: b0 0x0c(7-6)])=0b10, indicating dclk/dio output area. length msb lsb preamble sync word l field manchester/3-out-of-6 applicable [b0 0x07(3-2,1-0)] 1st block (*1) 2nd block optional block postamble a cc field ci field cc field ci field crc field data field crc field data field 1 byte 9 bytes 1 byte 1 byte 1 byte 1 byte 2 bytes 2 bytes max 112 bytes max 126 bytes 2-8 bits 10/18/ 32bits > n*2 bits crc applicable crc applicable c-a field extended block (*2) (*2) (*3) (*4) [b0 0x07] [b0 0x42] [b0 0x43] [b0 0x44] [b0 0x08] [b1 0x25-2e] [b0 0x05] [b0 0x7a/7b, 7d/7e] tx: automatic insertion rx: automatic detection, deletion
fedl7406-02 ML7406 30/104 (b) ci-field = 0x8d for tx, if 8 bytes extention format is used, set ext_pkt_mode[1:0]([pkt_ctrl1: b0 0x04(7-6)])=0b10. for rx, if rx_extpkt_off([pkt_ctrl1: b0 0x04(3)])=0b0, ML7406 recognizes ?ci-field? and rx operation is processed. *1: 1 st block is identical to normal format b.. *2: indicating tx fifo data storage area size. *3: indicating rx fifo data storage area size. *4: when rxdio_ctrl[1:0] ([dio_set: b0 0x0c(7-6)])=0b10, indicating dclk/dio output area. length msb lsb preamble sync word l field manchester/3-out-of-6 applicable [b0 0x07(3-2,1-0)] 1st block (*1) 2nd block opt i o n a l bl oc k postamble a cc field ci field cc field crc field data field crc field data field 1 byte 9 bytes 1 byte 1 byte 1 byte 1 byte 2 bytes 2 bytes max. 106 bytes max.126 bytes 2-8 bits 10/18/ 32bits > n*2 bits crc applicable crc a pp licable c-a field extended block sn field 4 bytes crc field 2 bytes crc applicable ci field (*2) (*2) (*3) (*2) (*4) [b0 0x07] [b0 0x42] [b0 0x43] [b0 0x44] [b0 0x08] [b1 0x25-2e] [b0 0x05] [b0 0x7a/7b, 7d/7e] tx: automatic insertion rx: automatic detection, deletion
fedl7406-02 ML7406 31/104 (3) format c (non wireless m-bus, general purpose format) by setting pkt_format([pkt_ctrl1: b0 0x04(1-0)])=0b10, format c, which is non wireless m-bus format, is selected. format c consists of 1 st block only, which has 2 bytes of crc. ?l-field? indicates packet length, which includes subsequent user data bytes, including crc bytes. the length of ?l-field? is defined by length_mode([pkt_ctrl2:b0 0x5(0]). data whitening function is supported. the following [] indicates register address [bank #, address]. *1 preamble length (n) is programmable by [txpr_len_h/l: b0 0x42/43] registers. *2 indicating tx fifo data strorage area size. *3 indicating rx fifo data storage area size. *4 when rxdio_ctrl ([dio_set: b0 0x0c(7-6)])=0b10, indicating dclk/dio output area. length msb lsb preamble sync word l field manchester/3-out-of-6 applicable [b0 0x07(3-2,1-0)] 1st block postamble data field crc field 1/2 bytes 0/1/2/4 bytes max2047 bytes 0/2-8 bits max 32bits > n*2 (*1) bit crc applicable whitening applicable [b0 0x08(0)] (*2) (*3) (*4) [b0 0x07] [b0 0x42] [b0 0x43] [b0 0x44] [b0 0x05] [b0 0x08] [b1 0x25-2e] [b0 0x05] [b0 0x7a/7b, 7d/7e] tx: automatic insertion rx: automatic detection, deletion
fedl7406-02 ML7406 32/104 crc function ML7406 has crc32,crc16 and crc8 function. crc is calculated and appended to tx data. crc is checked for rx data. the following modes are used for automatic crc function. fifo mode: rxdio_ctrl ([dio_set: b0 0x0c(7-6)]) = 0b00 dio mode: rxdio_ctrl ([dio_set: b0 0x0c(7-6)]) = 0b11 function control bit name / register tx crc setting tx_crc_en([pkt_ctrl2: b0 0x05(2)]) rx crc setting rx_crc_en([pkt_ctrl2: b0 0x05(3)]) crc length setting crc_len([pkt_ctrl2: b0 0x05(5-4)]) crc complement value off setting crc_comp_off([pkt_ctrl2: b0 0x05(6)]) crc polynomial setting [crc_poly3/2/1/0: b1 0x16/17/18/19] registers crc error status [crc_err_h/m/l: b0 0x13/14/15] registers any crc polynomials for crc32/crc16/crc8 can be specified. reset value is as follows: crc16 polynomial = x 16 + x 13 + x 12 + x 11 + x 10 + x 8 + x 6 + x 5 + x 2 + 1 (reset value) (note) crc result data can be inverted by crc complement value off setting,. crc data will be generated by the following circuits. by programming [crc_poly3/2/1/0] registers, any crc polynomials can be supported. generated crc will be transfer from the left most bit (s15). if data length is shorter than crc length (3 byt es of crc32 only), data ?0?s will be added for crc calculation. crc check result is stored in [crc_err_h/m/l] registers. unlike format c, format a/b can include multiple crc fields in one packet. for multiple crcs check results, crc value closest to l-field will be stored in crc_err[0] ([crc_err_l:b0 0x15(0)]). subsequent bit will be stored in crc_err from msb order. (note) :exclusive or crc polynomial circuits general crc polynomial can be programmed by below [crc_poly3/2/1/0] register setting. crc length can be set by crc_len. [crc_poly3/2/1/0] crc polynomial (b1 0x16) (b1 0x17) (b1 0x18) (b1 0x19) crc8 x 8 + x 2 + x + 1 0x00 0x00 0x00 0x03 x 16 + x 12 + x 5 + 1 0x00 0x00 0x08 0x10 x 16 + x 15 + x 2 + 1 0x00 0x00 0x40 0x02 crc16 x 16 + x 13 + x 12 + x 11 + x 10 + x 8 + x 6 + x 5 + x 2 + 1 0x00 0x00 0x1e 0xb2 crc32 x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 0x02 0x60 0x8e 0xdb crc_poly [ 14 ] crc_poly [ 0 ] crc_poly [ 1 ] crc_poly [ 2 ] crc_poly [ 13 ] input data s0 s1 s2 s3 s14 s15
fedl7406-02 ML7406 33/104 data whitening function (non wireless m-bus standard) ML7406 supports data whitening function. in packet format a/b, subsequent data followed by c-field can be processed data whitening. in packet format c, data whitening is applied from data field. data generated by the following 9 bit pseudo random sequence (pn9) will be ?xor? with tx data (encoded data if manchester or 3-out-of 6 coding is selected) before transmission. intialization value of the pn9 generation shift register can be defined by [wht_init_h/l: b1 0x64/65] registers. pn9 polynomial can be programmed with [wht_cfg: b1 0x66] register. function control bit name data whiteing setting enable wht_set ([data_set2: b0 0x08(0)]) data whiteing initiazation value wht_init[8:0] ([wht_init_h /l: b1 0x64(0)/65(7-0)]) whitening polynomia wht_cfg[7:0] ([wht_cfg: b1 0x66(7-0)]) in order to make feedback from s1 register, setting 0b1 to wht_cfg0 ([wht_cfg: b1 0x66(0)]). similaly in order to make feedback from s2 register, setting 0b1 to wht_cfg1 ([wht_ cfg: b1 0x66(1)]). other bits of [wht_cfg: b1 0x66] register has same function. two or more bits can be also set to 0b1. therefore any type of pn9 polinominal can be programmed. (note) :exclusive or whitening data generation circuits (generator polynomial: x 9 + x 5 + 1) general pn9 polynomial can be defined by [wht_cfg]. pn9 polynomial wht_cfg[7:0] [wht_cfg: b1 0x66] x 9 + x 4 + 1 0x08 x 9 + x 5 + 1 0x10 s8 s7 s6 s5 s4 s3 s2 s1 s0 whitening data
fedl7406-02 ML7406 34/104 syncword detection function ML7406 supports automatic syncword recognition function. by having two sets of syncword pattern storage area, it is possible to detect two different packet format (format a/b) which are defined by wireless m-bus. (for details, please refer to wireless m-bus standard) receiving packet format is indicate d by sw_det_rslt([stm_state:b0 0x77(5)]). in format c, it is possible to search for two syncwords but detected result is not indicated. 1) tx syncword pattern defined by syncword_sel ([data_set2: b0 0x08(4)]) will be selected. syncword length for tx is defined by sync_word_len[5:0] ([sync_w ord_len: b1 0x25(5-0)]). from high bit of each syncword pattern will be transmitted. syncword_sel tx syncword pattern 0 sync_word1[31:0] ([syncword1_set3/2/1/0: b1 0x27/28/29/2a]) 1 sync_word2[31:0] ([syncword2_set3/2/1/0: b1 0x2b/2c/2d/2e]) example) syncword patten and syncword length if the follwing registers are programmed, from higher bit of sync_word1[17:0] will be transmitted sequencially. [sync_word_len: b1 0x25]=0x12 syncword_sel ([data_set2: b0 0x08(4)]) = 0b0 if the following registers are programmed, from higher bit of sync_word2[23:0] will be transmitted sequencially. [sync_word_len: b1 0x25]=0x18 syncword_sel ([data_set2: b0 0x08(4)]) = 0b1 2) rx by setting syncword_sel and 2sw_det_en ([data_set2: b0 0x08(4,3)]), one syncword pattern waiting or two syncword patterns waiting can be selected as follows: packet format automatic detection is valid if 2sw_det_en=0b1 and format a or fromat b is selected by pkt_format[1:0] ([pkt_ctrl1:b0 0x04(1-0)]). 2sw_det_ en syncword_ sel syncword pattern during sync detection syncword detection operation automatic packet format detection data process after syncword 0 0 sync_word1[31:0] waiting for 1 pattern no process according to each format setting 0 1 sync_word2[31:0] waiting for 1 pattern no process according to each format setting 1 ? sync_word1[31:0] sync_word2[31:0] waiting for 2 patterns yes [format a or format b setting] if matched with sync_word1, then process as format a. if matched with sync_word2, then process as format b. [format c setting] process as format c
fedl7406-02 ML7406 35/104 length of syncword pattern can be defined by sync_wor d_len[5:0] ([sync_word_len: b1 0x25(5-0)]). in this case, syncword pattern defined by the length from low bit of sync_word1[31:0] or sync_word2[31:0] will be the pattern for checking. example) syncword length if the following registers are set, 18 bit of sync_wor d1[17:0] or sync_word2[17:0] will be reference pattern for the syncword detection. higher bits (bit31-18) are not checked. [sync_word_len: b1 0x25]=0x12 [sync_word_en: b1 0x26]=0x0f 32bit syncword pattern can be controlled by enabling/disabling by each 8bit, when receiving syncword. the following table describes enable/disable control and syncword pattern. sync_word* [sync_word_en] (b1 0x26) [31:24] [23:16] [15:8] [7:0] syncword detection operation 0000 no syncword detection 0001 d.c.(*1) on only [7:0] are valid. upon [7:0] detection, syncword detection. 0010 d.c. on d.c. only [15:8] are valid. upon [7:0] detection, syncword detection. 0011 d.c. on on [15:0] are valid. upon [7:0] detection, syncword detection. 0100 d.c. on d.c. only [23:16] are valid. upon [7:0] detection, syncword detection. 0101 d.c. on d.c. on [23:16] and [7:0] are valid. upon [7:0] detection, syncword detection. 0110 d.c. on on d.c. [23:8] are valid. upon [7:0] detection, syncword detection. 0111 d.c. on on on [23:0] are valid. upon [7:0] detection, syncword detection. 1000 on d.c. only [31:24] are valid. upon [7:0] detection, syncword detection. 1001 on d.c. on [31:24] and [7:0] are valid. upon [7:0] detection, syncword detection. 1010 on d.c. on d.c. [31:24] and [15:8] are valid. upon [7:0] detection, syncword detection. 1011 on d.c. on on [31:24] and [15:0] are valid. upon [7:0] detection, syncword detection. 1100 on on d.c. [31:16] are valid. upon [7:0] detection, syncword detection. 1101 on on d.c. on [31:16] and [7:0] are valid. upon [7:0] detection, syncword detection. 1110 on on on d.c. [31:8] are valid. upon [7:0] detection, syncword detection. 1111 on on on on whole [31:0] are valid. upon [7:0] detection, syncword detection. *1 d.c. stands for don?t care. *2 preamble pattern can be added to the syncword de tection conditions by rxpr_len[5:0]([sync_condition1: b0 0x45(5-0)]).
fedl7406-02 ML7406 36/104 field check function ML7406 has the function of caparing the 9 bytes following l-field (format a/b: start from c-field, format c: start from data-field) in a receiving packet. based on comparison with th e expected data, possible to generate interrupts (field check function). field check can be possible with the following register setting. when using this function, rxdio_ctrl[1:0] ([dio_set:b0 0x0c(7-6)] ) =0b00 (fifo mode) or 0b11 (data output mode 2) setting is required. function register rx data process setting when field check unmatched [c_check_ctrl: b0 0x1b(7)] field check interrupt setting [c_check_ctrl: b0 0x1b(6)] c-field detection enable setting [c_check_ctrl: b0 0x1b(4-0)] m-field detection enable setting [m_check_ctrl: b0 0x1c(3-0)] a-field detection enable setting [a_check_ctrl: b0 0x1d(5-0)] c-field code setting [c_field_code1: b0 0x1e] [c_field_code2: b0 0x1f] [c_field_code3: b0 0x20] [c_field_code4: b0 0x21] [c_field_code5: b0 0x22] m-field code setting [m_field_code1: b0 0x23] [m_field_code2: b0 0x24] [m_field_code3: b0 0x25] [m_field_code4: b0 0x26] a-field code setting [a_field_code1: b0 0x27] [a_field_code2: b0 0x28] [a_field_code3: b0 0x29] [a_field_code4: b0 0x2a] [a_field_code5: b0 0x2b] [a_field_code6: b0 0x2c] the following describes the relation between each comparison code and incoming rx data. [format a/b(wireless m-bus)] field check can be controlled by setting disabled/enabled for each comparison code (1 byte). if all specified field data (c-field/m-field/a-field) are matched, field checking matching will be notified. however, if c-field data and c_field_code5 are matched, even if other field data (m-field /a-field) are not matched, field check result will be notified as ?match?. msb preamble sync word l field 1st block a field c field m field 1 byte 1 byte 2 bytes 10/18/ 32bits over n*2 bit 6 bytes crc field 0/2 bytes c1: [c_field_code1: b0 0x1e] c2: [c_field_code2: b0 0x1f] c3: [c_field_code3: b0 0x20] c4: [c_field_code4: b0 0x21] c5: [c_field_code5: b0 0x22] a1. [a_field_code1: b0 0x27] a2. [a_field_code2: b0 0x28] a3. [a_field_code3: b0 0x29] a4. [a_field_code4: b0 0x2a] a5. [a_field_code5: b0 0x2b] a6. [a_field_code6: b0 0x2c] a1 a2 a3 a4 a5 a6 lsb m1. [m_field_code1: b0 0x23] m2. [m_field_code2: b0 0x24] m3. [m_field_code3: b0 0x25] m4. [m_field_code4: b0 0x26] m1 m2 m3 m4 c1 c2 c3 c4 c5
fedl7406-02 ML7406 37/104 check field comaprison code conditions for match c-field c_field_code1 or c_field_code2 or c_field_code3 or c_field_code4 or c_field_code5 if one of the 5 comparison code is matched m-field 1 st byte m_field_code1 or m_field_code2 if one of the 2 comparison code is matched. m-field 2 nd byte m_field_code3 or m_field_code4 if one of the 2 comparison code is matched. a-field a_field_code1/2/3/4/5/6 if comparison codes are matched. [format c] field check can be controlled by setting disabled/enabled fo r each comarison code (1 byte). if all specified field data (specified table below) are matched, field checking matching will be notified. however, if 1 st byte of data field and c_field_code5 are matched, even if other field data(from 2 nd byte of data field to 9 th byte of data field) are not matched, field check result will be notified as ?match?. check field comparison code conditions for match data-field 1 st byte c_field_code1 or c_field_code2 or c_field_code3 or c_field_code4 or c_field_code5 if one of the 5 comparison code is matched data-field 2 nd byte m_field_code1 or m_field_code2 if one of the 2 comparison code is matched. data-field 3 rd byte m_field_code3 or m_field_code4 if one of the 2 comparison code is matched. data-field 4 th byte a_field_code1 if comparison code is matched. data-field 5 th byte a_field_code2 if comparison code is matched. data-field 6 th byte a_field_code3 if comparison code is matched. data-field 7 th byte a_field_code4 if comparison code is matched. data-field 8 th byte a_field_code5 if comparison code is matched. data-field 9 th byte a_field_code6 if comparison code is matched. msb preamble sync word l field 1st block data field 1-2 byte 1 byte 10/18/ 32bits over n*2 bit c1: [c_field_code1: b0 0x1e] c2: [c_field_code2: b0 0x1f] c3: [c_field_code3: b0 0x20] c4: [c_field_code4: b0 0x21] c5: [c_field_code5: b0 0x22] a1. [a_field_code1: b0 0x27] a2. [a_field_code2: b0 0x28] a3. [a_field_code3: b0 0x29] a4. [a_field_code4: b0 0x2a] a5. [a_field_code5: b0 0x2b] a6. [a_field_code6: b0 0x2c] a1 a2 a3 a4 a5 a6 lsb m1. [m_field_code1: b0 0x23] m2. [m_field_code2: b0 0x24] m3. [m_field_code3: b0 0x25] m4. [m_field_code4: b0 0x26] m1 m2 m3 m4 c1 c2 c3 c4 c5 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte
fedl7406-02 ML7406 38/104 packet processing as a result of field checking by setting ca_rxd_clr ([c_check_ctrl: b0 0x1b(7)])=0b1, if the result of field check is unmatch, data packet will be aborted and wait for next packet data. storing number of unmatched packets unmatched packets can be counted up to max. 2047 packets and result are stored in [addr_chk_ctr_h: b1 0x62] and[addr_chk_ctr_l: b1 0x63]. this count value can be cleared by state_clr4 ([state_clr: b0 0x16(4)]).
fedl7406-02 ML7406 39/104 fifo control function ML7406 has on-chip tx_fifo(64byte) and rx_fifo(64byte). as tx/rx_fifo do not support multiple packets, packet should be processed one by one. if rx_fifo keeps rx packet and next rx packet is received, rx_fifo will be overwritten. it applies to tx_fifo as well. however tx fifo access error interrupt (int[20] group3) will be generated. when receiving, rx data is stored in fifo (byte by byte) and the host mcu will read rx data through spi. when transmitting, host mcu write tx data to tx_fifo through spi and transmitting through rf. writing or reading to fifo is through spi with burst access. tx data is written to [wr_tx_fifo: b0 0x7c] register. rx data is read from [rd_fifo: b0 0x7f] register. continuous access increments internal fifo counter automatically. if fifo access is suspended during write or read operation, address will be kept until the packet will be process again. therefore, whe n resuming fifo access, next data will be resumed from the suspended address. fifo control register are as follows: function register tx fifo full level setti ng [txfifo_thrh: b0 0x17] tx fifo empty level setting [txfifo_thrl: b0 0x18] rx fifo full level setting [rxfifo_thrh: b0 0x19] rx fifo empty level setting [rxfifo_thrl: b0 0x1a] fifo readout setting [fifo_set: b0 0x78] rx fifo data usafe status indication [rx_fifo_last: b0 0x79] tx packet length setting [tx_pkt_len_h/l: b0 0x7a/7b] rx packet length setting [rx_pkt_len_h/l: b0 0x7d/7e] tx fifo [wr_tx_fifo: b0 0x7c] fifo read [rd_fifo: b0 0x7f] tx ? rx procedure using fifo are as follows: [tx] i) tx data l-field value is set to [tx_pkt_len_h: b0 0x7a], [tx_pkt_len_l: b0 0x7b] register. if length is 1 byte, [tx_pkt_len_l] register will be transmitted. length can be set to length_mode([pkt_ctrl2: b0 0x05(0)]). ii) tx data is written to [wr_tx_fifo:b0 0x7c] register. (note) 1. if tx_fifo write sequence is aborted during transmission, state_clr0 [state_clr:b0 0x16(0)] (tx fifo pointer clear) must be issued. otherwise data pointer is kept in the lsi and the next packet is not processed properly. for example, tx fifo access error interrupt (int[20] group3) is generated. this interrupt can be generated when the next packet data is writren to the tx_fifo before transmitting previous packet data or tx_fifo overrun (fifo is written when no tx_fifo space) or underrun (attempt to transmit when tx_fifo is empty) 2. depending on the packet format, tx data length value is different. format a: length includs data area excluding l-field and crc data. format b: length includes data area excluding l-field. format c: length includes data area excluding l-field. [rx] i) l-field (length) is read from [rx_pkt_len_h: b0 0x7d], [rx_pkt_len_l: b0 0x7e] registers. ii) reading rx data from rx_fifo. when reading from rx_fifo, set fifo_r_sel([fifo_set: b0 0x78(0)])= 0b0. if fifo_r_sel=0b1 , tx_fifo will be selected. data usage value of rx_fifo is indicated by [rx_fifo_last: b0 0x79] register.
fedl7406-02 ML7406 40/104 (note) 1. if reading fifo data is terminated before reading a ll data, state_clr1 [state_clr: b0 0x16(1)] (rx fifo pointer clear) must be issued. otherwis e if rx_fifo is not cleared, the pointer controlling fifo data keeps the same status. next rx data will not be processed in the fifo properly. for example, when rx_fifo access error interrupt (int[12] group2) is generated. this interrupt occurs when rx_fifo overrun (data received when no space in rx_fifo) or underrun (reading empty rx_fifo). 2. if 1 packet data is kept in the rx_fifo, next rx data will be overwritten. if tx/rx pack is larger than fifo size, fifo access can be controlled by fifo-full trigger or fifo-empty trigger. (1) tx fifo usage notification function this function is to notice tx_fifo usage to the mcu using interrupt (sintn). if tx_fifo usage (un-transmitted data in tx_fifo) exceed the full level threshold set by [txfifo_thrh : b0 0x17] register, interrupt will generate as fifo-full interrupt (int[5] group1). if tx_fifo usage is smaller than empty level threshold set by [txfifo_thrl: b0 0x18] register, fifo-empty interrupt will generate as fifo-empty interrout (int[4] grou1). interrupt signal (sintn) can be output from gpio* or ext_clk pin. for output setting, please refer to [gpio1_ctrl: b0 0x4e], [gpio1_ctrl: b0 0x4f], [gpio2_ctrl: b0 0x50], [gpio3_ctrl: b0 0x51], [extclk_ctrl: b0 0x52] registers for output setting. (reference sequence) 1. set full level threshold and empy level threshold..each threshold should set as txfifo_thrh[5:0] ([txfifo_thrh:b0 0x17(5-0)]) > txfifo_thrl[5:0] ([txfifo_thrl:b0 0x18(5-0)]). and enabling full level threshold by txfifo_thrh_en([txfifo_thrh:b0 0x17(7)=0b1. 2. enabling fast_tx mode by fast_tx_en([rf_status_ctrl:b0 0x0a(5)])=0b1 and start writing tx data to the tx_fifo[wr_tx_fifo:b0 0x7c] until fifo-full interrupt (int[5] group1) occurs. 3. after fifo-full interrupt is generated, clear the interupt. then disabling full level threshold (txfifo_thrh_en= 0b0) and enabling empty level threshold (txfifo_thrl_en([txfifo_thrl:b0 0x18(7)])=0b1). 4. after fifo-empty interrupt (int[4] group1) is generated, clear the interupt. then disabling empty level threshold (txfifo_thrl_en=0b0) and enabling full level threshold (txfifo_thrh_ en=0b1). then resume writing tx data to the tx_fifo until next fifo-full interrupt occurs. 5. repeat 3.-4. until completion of tx. empty level (example 0x0f) full level (example 0x2e) 0 x 3f generate interrupt when tx data usage is smaller than empty level [fifo usage] time full level empty level tx data amount tx_fifo usage transition 0x0f 0x2e sintn signal tx data amount tx_fifo usage tx start timing by fast_tx trigger clear interrupt 0 x 00 generate interrupt when written data exceed full level
fedl7406-02 ML7406 41/104 (note) when skip disabling threshold level at sequece 3. or 4., depe nding on tx data read (phy block) and tx_fifo write timing through spi, in the middle of tx_fifo writing, unwiilling fifo-full interrupt or fifo-empty interrupt may occurs. (2) rx fifo usage notification function this function is to notify rx_fifo usage amount by using interru pt (sintn) to the mcu. if rx_fifo usage (un-read data in rx_fifo) exceed full level threshold defined by [rxfifo_thrh: b0 0x19] register, interrupt will generate as fifo-full interrupt (int[5] group1). after mcu read rx data from rx_fifo, un-read amount become smaller than empty level threshold defined by [rxfifo_thrl: b0 0x1a] register, interrupt will generated as fifo-empty (int[4] group1). interrupt signal (sintn) can be output from gpio* or ext_clk. for output setting, please refer to [gpio1_ctrl: b0 0x4e], [gpio1_ctrl: b0 0x4f], [gpio2_ctrl: b0 0x50], [gpio3_ctrl: b0 0x51], [extclk_ctrl: b0 0x52] registers. (reference sequence) 1. set full level threshold and empy level threshold..each threshold should set as rxfifo_thrh[5:0] ([rxfifo_thrh:b0 0x19(5-0)]) > rxfifo_thrl[5:0] ([rxfifo_thrl:b0 0x1a(5-0)]). and enabling full level threshold by rxfifo_thrh_en([rxfifo_thrh:b0 0x19(7)=0b1. 2. after issuing rx_on, wait fifo-full interrupt (int[5] group1) generation. 3. after fifo-full interrupt is generated, clear the interupt. then disabling full level threshold (rxfifo_thrh_en= 0b0) and enabling empty level threshold (rxfifo_thrl_en([rxfifo_thrl:b0 0x1a(7)])=0b1). and start reading rx data from rx_fifo [rd_fifo:b0 0x7f]. 4. after fifo-empty interrupt (int[4] group1) is generated, clear the interupt. then disabling empty level threshold (txfifo_thrl_en=0b0) and enabling full level threshold (txfifo_thrh_ en=0b1). then resume writing tx data to the tx_fifo until next fifo-full interrupt occurs. 5. repeat 3.-4. until completion of rx data read out. (note) when skip disabling threshold level at sequece 3. or 4., depe nding on rx data write (phy block) and rx_fifo read timing through spi, in the middle of rx_fifo reading, unwiilling fifo-full interrupt or fifo-empty interrupt may occurs. empty level (example 0x0f) full level (example 0x3e) 0x00 0 x 3f generate interrupt, when un-read data amount is less than empty level after read rx data from rx_fifo, [fifo usage] time rx data amount full level empty level rx data amount rx_fifo usage transition 0x0f 0x3e sintn signal generate interrupt, when rx data exceed full level, rx_fifo usage clear interrupt
fedl7406-02 ML7406 42/104 di o function using gpio0-3, ext_clk or sdi/sdo pins, tx/rx data can be input/output. pins can be configured by [gpio*_ctrl: b0 0x4e/0x4f/0x50/0x51], [extclk_ctrl: b0 0x52] and [spi/ext_pa_ctrl: b0 0x53] registers. data format for tx/rx are as follows: tx --- tx data (nrz or manchester/3-out-of-6coding) will be input. rx --- pre-decoded rx data or decoded rx data will be output. (selectable by [dio_set: b0 0x0c] register) dio function registers are as follows: function registers dio rx data output start setting [dio_set: b0 0x0c(0)] dio rx completion setting [dio_set: b0 0x0c(2)] tx dio mode setting [dio_set: b0 0x0c(5-4)] rx dio mode setting [dio_set: b0 0x0c(7-6)] (1) in case of using gpio*, ext_clk pins if gpio0-3 or ext_clk pins are used as dclk/dio, dclk/dio should be controlled as follow. (below dio/dclk vertical line part indicate output or input period) [tx] i) continuous input mode (from host) set txdio_ctrl[1:0] ([dio_set: b0 0x0c(5-4)]) =0b01. after tx_on(set_trx[3:0]([rf_status: b0 0x0b(3-0)])=0x9), dclk is output continuously. at falling edge of dclk, tx data is input from dio pin. tx data must be encoded data. (note) for details of timing, please refer to the ?tx? in the ?timing chart?. ii) data input mode (from host) set txdio_ctrl[1:0] ([dio_set: b0 0x0c(5-4)]) =0b10. after tx_on, dclk is output during data input period after syncword. tx data is input at falling edge of dclk through dio input. encoded tx data must be transferred from the host. preamble and syncwordis generated automatically according to the registers setting. dio(gpio0-3,ext_clk) tx_on command tx data dclk(gpio0-3,ext_clk) preamble syncword data-field trx_off command dio(gpio0-3,ext_clk) tx_on tx_on command tx data dclk(gpio0-3,ext_clk) preamble syncword data-field trxoff command tx_on
fedl7406-02 ML7406 43/104 preamble can be set by pb_pat([data_set1: b0 0x07(7)] and txpr_len[15:0] ([txpr_len_h/l: b0 0x42/43]). syncword can be set by syncword_sel([data_set1 : b0 0x08(4)), syncword_len[5:0] ([sync_word_ len: 1 0x25(5-0)]), sync_word_en* ([sync_word_en: b1 0x26(3-0)]), sync_word1[31:0] ([syncword1_ set3/2/1/0: b1 0x27/28/29/2a]), sync_word2[31:0] ([syncword2_set3/2/1/0: b1 0x2b/2c/2d/2e]). [rx] i) continuous output mode (to host) set rxdio_ctrl[1:0] ([dio_set: b0 0x0c(7-6)])=0b01. after rx_on (set_trx[3:0] ([rf_status: b0 0x0b(3-0)])=0x6) , dclk is output continuously. rx data (demodulated data) is output from dio pin at falling edge of dclk. rx data is not stored in rx_fifo. (note) for details of timing, please refer to the ?rx? in the ?timing chart?. ii) data output mode 1 (to host) set rxdio_ctrl[1:0] ([dio_set: b0 0x0c(7-6)]) =0b10. after syncword detection, rx data is buffered in rx_fifo. rx data buffering will continue until rx sync signal (sync) becomes ?l?. by setting dio_start ([dio_set: b0 0x0c(0)])=0b1, top data of buffered data will be output through dio interface (dio/dclk). (rx data is output at fa lling edge of dclk). howeve r, if dio_start setting is done after 64 byte timing, the top byte will be over written. if all buffered data is output until sync becomes ?l?, rx completion interrupt (int[8] group 2) will be generated. after rx completion, ready to receive next packet. (note) 1. rx data buffering in rx_fifo is accessed byte by byte. dio_start s hould be issued after 1 byte access time upon syncword detection. 2. this mode does not process l-field. field checking function is not supported. dio(gpio0-3,ext_clk) rx_on rx_on command rx data dclk(gpio0-3,ext_clk) preamble syncword data-field trx_off command dio(gpio0-3,ext_clk) rx_on rx_on command rx data dclk(gpio0-3,ext_clk) preamble syncword data-field trx_off command buffering to rx_fifo rx sync signal dio_start =0b1
fedl7406-02 ML7406 44/104 if dio_start is issued before syncword detection, data is not buffered in rx_fifo and rx data after syncword detection will be output at falling edge of dclk . in order to complete rx before sync becomes ?l?, dio rx completion setting (dio_rx_complete([dio_set: b0 0x0c(2)]=0b1) is necessary. after dio_rx_complete setting, ready to receive the next packet. iii) data output mode 2 (to host) set rxdio_ctrl[1:0] ([dio_set: b0 0x0c(7-6)])=0b11. only data-field of rx data is buffered in rx_fifo. rx data indicated by l-field is stored in rx_fifo. by dio_start([dio_set: b0 0x0c(0)])=0b1, top data of buffered data will be output through dio interface (dio/dclk). (rx data is output at falling edge of dclk). however, if dio_start setting is done after 64 byte timing, the top byte will be overwritten. if all data indicated by l-field is output, rx completion interrupt (int[8] group2) will be generated. after rx completion, ready to receive next packet. length information is stored in [rx_pkt_len_h/l: b0 0x7d/7e] registers. this mode support fileld check function. (note) rx data buffering in rx_fifo is byte by byte access. dio_start should be issued after elapsed time from syncword detection to l-field length + over 1byte access time. dio(gpio0-3,ext_clk) rxon rx_on command rx data dclk(gpio0-3,ext_clk) preamble syncword data-field trx_off command dio_start issue dio(gpio0-3,ext_clk) rxon rx_on command rx data dclk(gpio0-3,ext_clk) preamble syncword data-field trxoff command buffering to rx_fifo rx sync signal dio_start=0b1 l-field dio_rx_complete =0b1
fedl7406-02 ML7406 45/104 (2) in case of using sdi/sdo pin (sharing with spi interface) if sdi and sdo pins are used dclk/dio, dclk/dio is controlle d as follow. (below dio/dclk vertical line part indicate output or input.) both sdo_cfg and sdi_cfg ([spi/ext_pa_ctrl:b0 0x53 (5,4)]) should be set 0b1. [tx] i) continuous input mode (from host) set txdio_ctrl[1:0] ([dio_set: b0 0x0c(5-4)])=0b01 after tx_on (set_trx[3:0] ([rf_status: b0 0x0b(3-0)])=0x9) , during scen pin is ?h?, dclk is output from sdo pin. tx data can be input from sdi pin at falling edge of dclk. tx data must be encoded data. after trx_off is issued (set_trx[3:0] ([rf_status: b0 0x0b(3-0)])=0x8), input data from dio pin are not valid. during dclk output, if scen pin becomes ?l?, dclk output will stop. (spi access has priority) (note) not to access spi until tx completion. during packet transmission, if spi access is attempted by the host, tx data error can be expected. ii) data input mode (from host) set txdio_ctrl[1:0] ([dio_set: b0 0x0c(5-4)])=0b10. after tx_on, when scen is ?h?, dclk is output from sdo pin during data input period after syncword. at falling edge of dclk, tx data should be input to sdi from the host. after trx_off is issued (set_trx[3:0] ([rf_status: b0 0x0b(3-0)])=0x8), tx data/clock input/output are invalid. duri ng dclk output period, if scen becomes ?l?, dclk output will stop. (spi access has a priority) (note) not to access spi until tx completion. during packet transmission, if spi access is attempted by the host, tx data error can be expected. txon tx_on command tx data preamble syncword data-field trx_off command scen dio(sdi) txon tx_on command tx data dclk(sdo) preamble syncword data-field trx_off command scen dio(sdi) dclk(sdo)
fedl7406-02 ML7406 46/104 [rx] i) continuous output mode (to host) set rxdio_ctrl[1:0] ([dio_set: b0 0x0c(7-6)])=0b01. after rx_on (set_trx[3:0]([rf_status: b0 0x0b(3-0)])=0x6) issued, during scen is ?h? period, dclk is output from sdo pin, rx data is output from sdi pin at falling edge of dclk. after trx_off issuing(set_trx[3:0] ([rf_status: b0 0x0b(3-0)])=0x8), dclk/dio output will stop. even if dc lk/dio are output, when scen becomes ?l?, dclk/dio will stop. (spi access has a higher priority) (note) not to access spi until rx completion. during packet receiption, if spi access is attemped by the host, rx data error can be expected. it is recommended ii) data ouput mode 1 or data output mode 2 (to host) set rxdio_ctrl[1:0] ([dio_set: b0 0x0c(7-6)])=0b10/11 after rx_on, rx data upon syncword (output mode 1) or rx data upon l-fileld (output mode 2) is buffered in rx_fifo. during scen is ?h?, by dio_start([dio_set: b0 0x0c(0)])=0 b1, top data of buffered data will be output through dio interface (dio/dclk). (rx data is output at falling edge of dclk). other output condition is same as the case of using gpio:/ect_clk pins. after trx_off isuing, dclk/dio output will stop. even during dclk/dio are output period, if scen becomes ?l?, dclk/dio output will stop. (spi access has a priority) (in case of data output mode1) (note) not to access spi until rx completion. during packet receiption, if spi access is attemped by the host, rx data error can be expected. rx_on rx_on command rx data preamble syncword data-field trx_off command scen rxon rx_on command rx data preamble syncword data-field trx_off command scen dio_rx_complete =0b1 dio_start =0b1 dio(sdi) dclk(sdo) dio(sdi) dclk(sdo)
fedl7406-02 ML7406 47/104 (3) dclk output method in data output mode 2, decoded data is output. therefore, the dclk output section in a output interval changes with the coding method. dclk output section is as follows. in othe modes, undecoded data is input or output. dclk is output continuously. then, it is not depend on the coding method. i) data output mode 2 ii) tx continuous input mode or rx continuous mode iii) tx data input mode / rx data output mode1 clock output (8 cycle) output interval nrz : 8 cycle manchester : 16 cycle 3 out of 6 : 12 cycle output interval dclk 1 cycle=1/data rate[bps] (*) the nuber of cycle per 1 byte nrz : 8 cycle manchester : 16 cycle 3 out of 6 : 12 cycle dclk dclk tx: the timing during transmitting the last 2 bit syncword rx: dio_start issue 1 cycle=1/data rate[bps] 1 cycle=1/data rate[bps] (*) the nuber of cycle per 1 byte nrz : 8 cycle manchester : 16 cycle 3 out of 6 : 12 cycle
fedl7406-02 ML7406 48/104 timer function w ake-up timer ML7406 has automatic wake-up function using wake-up timer. the following operations are possible by using wake-up timer. ? upon timer completion, automatically wake-up from sleep state. after wake-up operation can be selected as rx_on state or tx_on state by wakeup_mode ([sleep/wu_set: b0 0x2d(6)]). ? by setting wut_1shot_mode ([sleep/wu_set: b0 0x2d(7)]), continuous wake-up operation (interval operation) or one shot operation can be selected ? in interval operation, if rx_on /tx_on state is caused by wake-up timer, continuous operation timer is in operation.. ? after moving to rx_on state by wake-up timer, when continuous operation timer completed, move to sleep state automatically. however, if syncword is detected before timer completion, rx_on state will be maintained. in this case, ML7406 does not go back to sleep state automatically. sleepsetting (sleep_en[sleep/wu_set: b0 0x2d(0)])=0b1) is necessary to go back to sleep st ate. however if rxdone_ mode[1:0]([rf_status_ctrl:b0 0x0a(3-2)]) =0b11, after rx completion, move to sleep state automatically. ? after moving to tx_on state by wake-up timer, when continuous operation timer completed, go back to sleepstate automatically. ? after wake-up by combining with high speed carrier checking mode, cca is automatically performed, if idle is detected, able to move to sleep state immediately. for de tails, please refer to the ?(3) high speede carrier detection mode?. ? by setting wu_clk_source ([sleep/wu_set:b0 0x2d(2)]), clock source for wake-up timer are selectable from ext_clk pin or on-chip rc osc. wake-up intervalm, wake-up timer interval and continuous operation timer can be calculated in the following formula. wake-up interval [s] = wake-up timer interval [s] + continuous operation timer [s] wake-uptimer interval [s] = wake-up timer clock cycle * division setting ([wut_clk_set: b0 0x2e(3-0)]) * wake-up timer interval setting ([wut_interval_h/l: b0 0x2f/0x30]) continuous operation timer [s] = wake-up timer clock cycle * division setting([wut_clk_set: b0 0x2e(7-4)]) * continuous operation timer setting ([wu_duration: b0 0x31]) (note) ? in case of moving to tx_on state after wake-up, move to sleep state when timer completed even in the middle of transmission. continuous oeration timer should be set in such manner that timer completing after tx completion. ? wudt_clk_set[3:0] ([wut_clk_set: b0 0x2e(7-4)]) and wut_clk_set[3:0] ([wut_clk_set: b0 0x2e (3-0)]) can be set independently. ? minimum value for wake-up timer interval setting ([wut_interval_h/l: b0 0x2f/0x30]) is 0x02. and minimum value for continuous operation timer setting ([wu_duration: b0 0x31]) is 0x01. ? be noted that the syncword detection is not issued when in dio mode with rxdio_ctrl([dio_set: b0 0x0c(7-6)])=0b01. therefore, when continuous operation timer completed, forcibly move to sleep state.
fedl7406-02 ML7406 49/104 (1) interval operation [rx] after wake-up, rx_on state. if continuous operation timer completed before syncword detection, automatically return to sleep state. if syncword detected, continue rx_on. after rx completion, continue operation defined by rxdone_ mode[1:0] ([rf_status_ ctrl: b0 0x0a(3-2)]) . [tx] after wake-up, tx_on state. after tx completion, continue operation defined by txdone_mode[1:0] ([rf_status_ ctrl: b0 0x0a(1-0)]) . if continuous operation timer completed, automatically return to sleep state. so continuous operation timer has to be set so that timer completion occur after tx completion. rxon txon wake-up timer wake-up timer enable setting continuous operation timer wake-up timer operation range [wut_interval_h/l: b0 0x2f/0x30] lsi state sleep rxon continuous operation timer range [wu_duration: b0 0x31] before continuous operation timer completion, syncword detected. a fter rx completion, move to sleep state by sleep command. *1 if not issuing sleep command, continue operation defined by rxdone_mode[1:0] sleep rxon sleep rxon sleep *1 rxon sleep rxon rxon txon wake-up timer wake-up operation enables setting continuous operation timer wake-up timer operation period [wut_interval_h/l: b0 0x2f/0x30] lsi state continuous operation timer range [wu_duration: b0 0x28] tx completion and move to idle state. in case of txdone_mode[1:0]=0b00 continuous operation timer completion, move to sleep state. sleep txon tx data write to tx_fifo sleep idle txon sleep idle txon idle a fter wake-up timer completion , move to rx_on state. continuous operation timer completion move to sleep state. [sleep/wu_set: b0 0x2d(6-4)]=0b011 [sleep/wu_set: b0 0x2d(6-4)]=0b111
fedl7406-02 ML7406 50/104 (2) 1 shot operation [rx] after wake-up timer completion, move to rx_on state. an d continue rx_on state. move to sleep state by sleep command. if wake-up timer interval ([wut_interval_h/l: b0 0x2f/0x30]) is maintained, after re-issuing sleep command, 1 shot operation will be activated again. if rx completed during rx_on, continue operation defined by rxdone_ mode[1:0] ([rf_status_ ctrl: b0 0x0a(3-2)]) . same manner in tx_on state. (3) combination with high speed carrier detection [interval operation] after wake-up timer completion, move to rx_on state. then perform cca. if no carrier detected, automatically move to sleep state. if carrier detected, maintaining rx_on state an d perform suncword detection. if continuous operation timer completed before syncword detection, automatically move to sleep state. and if syncword detected, continue rx_on state state. rxon txon wake-up timer wake-up operation enable setting continuous operation timer wake-up timer operation range [wut_interval_h/l: b0 0x2f/0x30] lsi state a fter sleep command, move to sleep state. sleep rxon sleep rxon wake-up timer completion and move to rxon state rx_on is maintained if sleep command is not issued. rxon txon wake-up timer wake up operation enable setting continuous operation timer wake-up timer operation range [wut_interval_h/l: b0 0x2f/0x30] lsi state sleep rxon continuous operation timer range [wu_duration: b0 0x28] syncword detection before continuous operation timer completion a fter rx completion, move to sleep state by command. sleep rxon sleep rxon sleep rxon sleep rxon no carrier detection, and move to sleep state. carrier detected and continue rxon. continuous operation timer completion. and move to sleep state. [sleep/wu_set: b0 0x2d(7-4)]=0b1011 [sleep/wu_set: b0 0x2d(7-4)]=0b0011 fast_det_mode_en([cca_ctrl: b0 0x39(3)])=0b1
fedl7406-02 ML7406 51/104 [1 shot operation] after wake-up timer completion, move to rx_on state. and perf orm cca to check carrier. if no carrier detected, go back to sleep state automatically. after wake-up timer completion, wake-up to check the carrier again. if carrier is detected, continue rx state. able to go back to sleep by setting sleep parameters. general purpose timer ML7406 has general purpose timer. 2 channel of timer are able to function independently. clock sources, timer setting can be programmed independently. when timer is completed, general purpose timer 1 interrupt (int[22] group3) or general purpose timer 2 interrupt (int[23] group3) will be generated. general timer interval can be programmed as the following formula. general purpose timer interval[s] = general purpose timer clock cycle * division setting ([gt_clk_set: b0 0x33]) * general purpose timer interval setting ([gt1_timer: b0 0x34] or [gt2_timer: b0 0x35]) by setting gt2/1_clk_source ([gt_set: b0 0x32(5,1)]), clock sources for general purpose timer can be selectable from wake-up timer clock or 2mhz. rxon txon wake-up timer wake-up operation enable setting continuous operation timer wake-up timer operation range [wut_interval_h/l: b0 0x2f/0x30] lsi state sleep rxon by sleep command go to sleep state. sleep rxon sleep sleep no carrier detected. go to sleep state carrier detected, continue rxon sleep rxon [sleep / wu_set: b0 0x2d(7-4)]=0b1011 fast_det_mode_en([cca_ctrl: b0 0x39(3)])=0b1
fedl7406-02 ML7406 52/104 frequency setting function c hannel frequency setting maximum 256 channels can be selected (ch#0 -ch#255) by the following resisters. frequency register tx [txfreq_i: b1 0x1b], [txfreq_fh: b1 0x1c], [txfreq_fm: b1 0x1d] and [txfreq_fl: b1 0x1e] ch#0 frequency rx [rxfreq_i: b1 0x1f], [rxfreq_fh: b1 0x20], [rxfreq_fm: b1 0x21] and [rxfreq_fl: b1 0x22] channel space - [ch_spac e_h: b1 0x23] and [c h_space_l: b1 0x24] channel setting - [ch_set: b0 0x09] (1) channel frequency setting overview [channel frequency setting] using above registers, channel frequency is defined as following formula. channel frequency = i) ch#0 frequency + ii) channel sp ace * iii) channel setting [channel frequency allocation image] (note) the channel frequency to be selected must meet the follo wing conditions. if the following conditions cannot be met, please change channel #0 frequency or use other channels. if this formula cannot be met, expected frequency is not functional or pll may not be locked. tx: (f mck1 *n + 500khz ) channel frequency (f mck1 *(n+1) ? 500khz ) rx: (f mck1 *n +2.2mhz ) channel frequency (f mck1 *(n+1) ) f mck1 : master clock frequency n = integer unusable frequency usable frequency (f mck1 n ) frequency (f mck1 (n+1)) frequency ii) channel space setting i) ch#0 frequency setting channel no. ? 0 1 2 3 n 255 iii) channel setting (setting nth channel) a
fedl7406-02 ML7406 53/104 [calculation example of above ?a? range] condition: master clock 26mhz, n=33 tx:(26*33+0.5)mhz channel frequency to be used (26*(33+1)-0.5) 858.5mhz channel frequency to be used 883.5mhz rx:(26*33+2.2)mhz channel frequency to be used (26*(33+1)-2.2) 860.2mhz channel frequency to be used 881.8mhz (note) ?ch#0 frequency (hz)? and ?channle space (hz)? may have error (hz). then the ?channel frequency error (hz)? is defined as following formula. channel frequency error (hz) = ch #0 frequency error (hz) + channel space error (hz)* channel setting when changing ?channel frequency? by setting ?channel setting? without ?ch#0 frequency? change, the ?channel frequency error? will become larger than by setting both ?ch#0 frequency? and ?channel setting?. if the ?channle frequency error? is larger than expection, please consider to change ?ch#0 frequency?.
fedl7406-02 ML7406 54/104 (2) channel #0 frequency setting tx frequency can be set by [txfreq_i: b1 0x1b], [txfreq_fh: b1 0x1c], [txfreq_fm: b1 0x1d] and [txfreq_fl: b1 0x1e]. rx frequency can be set by [rxfreq_i: b1 0x1f], [rxfreq_fh: b1 0x20], [rxfreq_fm: b1 0x21] and [rxfreq_fl: b1 0x22]. channel #0 frequency setting value can be caluculated using the following formula. ref rf f f i = (integer part) 20 2 ? ? ? ? ? ? ? ? ? ? ? ?= i f f f ref rf (integer part) here rf f :channel #0 frequency ref f :pll reference frequency (=master clock frequency: f mck1 ) i :integer part of frequency setting f :fractional part of frequency setting i (hex) is set to [txfreq_i: b1 0x1b], [rxfreq_i: b1 0x1f] registers. f (hex.) is set to the following registers. for tx, from msb, set in order of [txfreq_fh: b1 0x1c], [txfreq_fm: b1 0x1d], [txfreq_fl: b1 0x1e] registers. for rx, from msb, set in order of [rxfreq_fh: b1 0x20], [rxfreq_fm: b1 0x21], [rxfreq_fl: b1 0x22] registers. frequency error ( err f ) is calculated as follows : rfref err ff f if ?? ? ? ? ? ? ? += 20 2 [example] when set tx channel #0 frequency to 868mhz (master clock 26mhz), the calculations are as follows. m h z mhz i 26 868 = (integer part) =33(0x21) 20 2 26 868 ? ? ? ? ? ? ? ? = i mhz mhz f (integer part)=403298(0x062762) [txfreq_i: b1 0x1b] = 0x21 [txfreq _fh: b1 0x1c] = 0x06 [txfreq _fm: b1 0x1d] = 0x27 [txfreq _fl: b1 0x1e] = 0x62 frequency error err f is as follows: hz mhz mhz f err 45.11 868 26 2 403298 33 20 ?= ?? ? ? ? ? ? ? +=
fedl7406-02 ML7406 55/104 (3) channel space setting channel space can be set by [ch_space_h: b1 0x23], [ch_space_l: b1 0x24] registers. hexadecimal values calculated in the following formula should be set to [ch_space_h: b1 0x23], [ch_space_l: b1 0x24] registers. (msb->lsb order) channel space is from the center frequency of give n channel to adjacent channel center frequency. channel space setting value can be calculated using the following formula: 20 2 _ ? ? ? ? ? ? ? ? ? ? ? = ref sp f f space ch (integer part) here :_ space ch channel space setting : sp f channel space [mhz] : ref f pll reference frequency (=master clock frequency : f mck1 ) [example] when set channle space to 60khz (master clock 26mhz), the calculation is as follows. 20 2 26 06.0 _ ? ? ? ? ? ? ? = mhz mhz space ch (integer part) = 2419 (0x0973) [ch_space_h: b1 0x23] = 0x09 [ch_space_l: b1 0x24] = 0x73
fedl7406-02 ML7406 56/104 if frequency setting in order to support various data rate , rx filters have to be optimised. the rx filter can be selected according to the if frequency. if frequency is set by [if_freq_h: b0 0x54],[if_freq_l: b0 0x55] registers. if frequency corresponds to each data rate must be selected as below. data rate 4.8kbps 32.768kbps 50kbps 100kbps if frequency 500khz 500khz 500khz 720khz for other data rate, please refer to ?initialization table?. if cca is used to detect channel carrier power, required rx filter bandwidth may be different. [if _freq_cca_h: b1 0x56] and [ if_freq_cca_l: b1 0x57] registers must be used for cca purpose. if frequency must be set according to the if frequency. if frequency setting value can be calculated using the following formula: 20 2 )2/( _ ? ? ? ? ? ? ? ? ? ? ? = ref if f f freqif (integer part) here freqif _ : if frequency setting : if f if frequency [mhz] : ref f pll reference frequency (=master clock frequency: f mck1 ) [example] when set if frequency to 720khz (master ckock 26mhz), the calculation is as follows. if_freq= {(0.72mhz 2) 26mhz} 2 20 (integer part) = 14518 (0x38b6) [if_freq_h: b0 0x54] = 0x38 [if_freq_l: b0 0x55] = 0xb6 bpf frequency band setting for normal operation (including afc) and cca operation, optimized bpf setting to [bpf_co: b0 0x5c] and [bpf_co_cca: b0 0x5d] registers are necessary. as indicated below table, proper value correspond to each data rate, must be programmed. normal case [bpf_co: b0 0x5c] cca [bpf_co_cca: b0 0x5d] data rate [kbps] [drate_set: b0 0x06] coefficient setting value coefficient setting value 4.8 0b0010 1.44 0xb8 1.44 0xb8 32.768 0b1000 1.44 0xb8 1.44 0xb8 50 0b1010 1.44 0xb8 1.44 0xb8 100 0b1011 1 0x80 1 0x80
fedl7406-02 ML7406 57/104 modulation setting ML7406 supports gfsk modulation and fsk modulation. (1) gfsk modulation setting by setting gfsk_en([data_set1: b0 0x07(4)])=0b1, gfsk m ode can be selected. in gfsk modulation, frequency deviation can be set by [gfsk_dev_h: b1 0x30] and [gfsk_dev_l: b1 0x31] registers and gasusiaan filter can be set by [fsk_dev0_h/gfil0: b1 0x32] - [fsk_dev3_h/gfil6: b1 0x38] registers. i) gfsk frequency deviation setting f_dev value can be calculated as the following formula: 20 2 _ ? ? ? ? ? ? ? ? ? ? ? = ref dev f f devf (integer part) here devf _ : frequency deviation setting : dev f frequency deviation [mhz] : ref f pll reference frequency (= master clock frequency: f mck1 ) [example] when set frequency deviation to 50kh (master clock 26mhz), the calculation is as follows. f_dev = {0.05mhz 26mhz} 2 20 (integer value) = 2016 (0x07e0) [gfsk_dev_h: b1 0x30] = 0x07 [gfsk_dev_l: b1 0x31] = 0xe0 ii) gaussian filter setting bt value of gaussian filter and setting value to related registers are shown in the below table. bt value register 0.5 1.0 [fsk_dev0_h/gfil0: b1 0x32] 0x49 0x00 [fsk_dev0_l/gfil1: b1 0x33] 0xa7 0x10 [fsk_dev1_h/gfil2: b1 0x34] 0x0f 0x04 [fsk_dev1_l/gfil3: b1 0x35] 0x14 0x0d [fsk_dev2_h/gfil4: b1 0x36] 0x19 0x1e [fsk_dev2_l/gfil5: b1 0x37] 0x1d 0x32 [fsk_dev3_h/gfil6: b1 0x38] 0x1e 0x3c (note) gfsk filter coefficient setting register and fsk frequency deviation setting register are common. in gfsk mode, filter coefficient applies to this register. in fsk mode, frequency deviation applies to this register.
fedl7406-02 ML7406 58/104 (2) fsk modulation setting by setting gfsk_en([data_set1: b0 0x07(4)])=0b0, fsk mode can be selected. fine frequency deviation can be set by [fsk_dev0_h/gfil0: b1 0x32] to [fsk_dev4_l: b1 0x3b] registers. by adjusting [fsk_tim_adj4-0: b1 0x3c-40] registers, fsk timing can be fine tuned. frequency deviation setting timing setting symbol register name address function symbol register name address function i fsk_fdev0_h/gfil0 fsk_fdev0_l/gfil1 b1 0x32/33 i fsk_tim_adj4 b1 0x3c ii fsk_fdev1_h/gfil2 fsk_fdev1_l/gfil3 b1 0x34/35 ii fsk_tim_adj3 b1 0x3d iii fsk_fdev2_h/gfil4 fsk_fdev2_l/gfil5 b1 0x36/37 iii fsk_tim_adj2 b1 0x3e iv fsk_fdev3_h/gfil6 fsk_fdev3_l b1 0x38/39 iv fsk_tim_adj1 b1 0x3f v fsk_fdev4_h fsk_fdev4_l b1 0x3a/3b frequency deviation resolution: approx.25hz v fsk_tim_adj0 b1 0x40 modulation timing 4.3mhz/13mhz counter value (*1) (*1) modulation timing resolution can be changed by fsk_clk_set ([fsk_ctrl: b1 0x2f(0)]). (note) gfsk filter coefficient setting register and fsk frequency deviation setting register are common. in gfsk mode, filter coefficient applies to this register. in fsk mode, frequency deviation applies to this register. tx_fsk_pol ([data_set1:b0 0x07(6)]) = 0b0 setting f f 1 output i ii iii v i iv 0 output i iii ii iv v i iii ii iv i ii iii iv i ii ii iii iii iv iv v v
fedl7406-02 ML7406 59/104 rx related function afc fun ction ML7406 supports afc function. frequency deviation (max85ppm) between remote device and local device can be compensated by this function. using this function, stable rx sensitivity and interference blocking performance can be achieved. this function can be enabled by setting afc_en([afc/gc_ctrl: b1 0x15(7)])=0b1. energy detection value (ed value) acquisition function ML7406 supports calculate energy detection value (ed valu e) based on receive signal strength indicator (rssi). ed value acquisition can be enabled by setting ed_calc_en ([ed_ctrl: b0 0x41(7)])=0b1 and as soon as trnasition to rx_on state, automatically start acquiring ed value. during rx_on state, ed value constantly updated. ed value is not rssi value at given timing, but average values. number of average times can be specified by ed_avg[2:0] ([ed_ctrl: b0 0x41(2-0)]). during diversity operation, di v_ed_avg[2:0] ([2div_mode: b1 0x48(2-0)]) is used for setting. after acquiring specified average ed value, ed_done([ed_ctrl: b0 0x41(4)]) becomes ?0b1? and ed_value[7:0] ([ed_rslt: b0 0x3a]) is updated. ed_done bit will be cleared if one of the following conditions are met. 1. gain is switched. 2. once stopping ed value acquisition and then resume it. 3. antenna is switched. (when diversity is enabled) timing from ed value starting point to ed value acquisition is calculated as below formula. ed value average time = ad conversion time (16 s/17.8 s) * number of average times. (note) ad conversion time can be set by adc_clk_set([adc_clk_set: b1 0x08(4)]). reset value is 2mhz and ad conversion timer is 16 s. the timing example is as follows: [condition] set adc_clk_sel([adc_clk_sel: b1 0x08(4)])=0b1 (2mhz) set ed_avg[2:0] ([ed_ctrl: b0 0x41(2-0)])=0b011 (8 times averaging) rssi value (internal signal) ad conversion (16 s/18.5 s) ed_done ([ed_ctrl:b0 0x41(4)]) ed value calculation execution flag (internal signal) ed_value [ed_rslt: b0 0x3a] ed value averaging period (16 s8=128 s) rssi 1 ed 1-8 invalid compensation and averaging ed 2-9 constantly update by moving average ed 3-10 rssi 2 rssi 3 rssi 4 rssi 5 rssi 6 rssi 7 rssi 8 rssi 9 rssi 10
fedl7406-02 ML7406 60/104 diversity function ML7406 supports two antenna diversity function. while setting 2div_en([2div_ctrl: b0 0x48(0)])=0b1, as soon as rx_on is set, diversity mode will start. when diversity mode is started, and upon rx data detection, each ed value will be acquired by switching two antennas. and then antenna with higher ed value will be selected automatically. as diversity uses preamble data for ed value acquisition, longer preamble length is desirable. if preamble is t oo short, accurate ed values may not be obtained. the timing example is as below. ed values acquired by the diversity operation are stored in [ant1_ed: b0 0x4a] and [ant2_ed: b0 0x4b] registers and antenna diversity result is indicated at 2div_rslt[2:0] ([2div_rslt: b0 0x49(1-0)]) when syncword is detected. in diversity operation, the number of ed average times is specified by 2div_ed_avg[2: 0]([2div_mode: b1 0x48(2:0)]). search time for each antenna is defined by [2div_search1: b1 0x49] and [2div_search2:b1 0x4a] registers. and its time resolution can be defined by search_time_set([2div_search1: b1 0x49(7)]). if diversity search completion interrupt (int[10] group2) is cleared, ed values and antenna diversity result are cleared. (note) when an incorrect diversity completion caused by errornous detection due to thermal noize, ML7406 resume antenna diversity automatically. but when receiving a desired signal duri ng the process of errounous detection, ed value obtained by [ant1_ed:b0 0x4a] or [ant2_ed:b0 0x4b] may indicate a low value different from the actual input level. if this event occures, the actual ed value of desired signal can be achibed by reading [ed_rslt:b0 0x3a] registers after syncword detection interrupt (int[13] group2) generation. length preamble sync word rx_on rx packet ant_sw ant1: ed value search ant2: ed value search antenna selection search_time1 ([2div_search1: b1 0x49(6-0)]) ant1/ant2 search is repeated search_time2 ([2div_search2: b1 0x4a(6-0)]) update ant rslt and ed values [2div_rslt: b0 0x49(1-0)]) [ant1_ed:b0 0x4a] [ ant2 ed:b0 0x4b ] data int[10] (diversity search completion) [int_source_grp2: b0 0x0e]
fedl7406-02 ML7406 61/104 (1) antenna switching function by using [2div_ctrl: b0 0x48], [ant_ctrl: b0 0x4c], [spi/ext_pa_ctrl: b0 0x53] registers, tx-rx signal selection (trx_sw), antenna switching signal (ant_sw), external pa control signal(dcnt) can be controlled. ML7406 can support both spdt and dpdt antena swith control. ant_sw signal and trx_sw signal output considion for each antenna switch are explained below. dpdt switch set 2port_sw([2div_ctrl: b0 0x48(1)])=0b1, ant_ctrl1([2div_ctrl: b0 0x48(5)])=0b0. ant_sw, trx_sw output condition of each idle, tx, rx state are as follow. (default setting) if inv_trx_sw([2div_ctrl: b0 0x48(2)])=0b1, polarity of ant_sw and trx_sw are reversed. inv_trx_sw=0b0 (default setting) inv_trx_sw=0b1 (reversed polarity) tx/rx state ant_sw trx_sw ant_sw trx_sw description idle h l l h idle state tx l h h l tx state h l l h when diversity disable or initial condition when diversity enable is set ([2div_ctrl: b0 0x48(0)]=0b1). rx l/h h/l h/l l/h if diversity enable is set, during searching, (ant_sw=h, trx_sw=l) and (ant_sw=l, trx_sw=h) are switched alternatively. after diversity completion, fix to one of the condition. spdt switch set 2port_sw([2div_ctrl: b0 0x48(1)])=0b0, ant_ctrl1([2div_ctrl: b0 0x48(5)])=0b0. ant_sw, trx_sw output condition of each idle, tx, rx state are as follow. (default setting) if inv_trx_sw([2div_ctrl: b0 0x48(2)])=0b1, polarity of ant_sw and trx_sw are reversed. inv_trx_sw([2div_ctrl: b0 0x48(2)])=0 (default setting) inv_trx_sw([2div_ctrl: b0 0x48(2)])=1 (polarity reverse) tx/rx condition ant_sw trx_sw ant_sw trx_sw description idle l l l h idel state tx l h l l tx state l l l h when diversity disable or initial condition when diversity enable is set ([2div_ctrl: b0 0x48(0)]=0b1). rx h/l l h/l h if diversity enable is set,during searching (ant_sw=h and (ant_sw=l) is switched alternatively. after diversity completion , fix to one of the condition.
fedl7406-02 ML7406 62/104 in the above setting, if inv_ant_sw([2div_ctrl: b0 0x48(3)])=0b1, ant_ctrl1([2div_ctrl: b0 0x48(5)])=0b1 are set, polarity of ant_sw pin is reversed. inv_ant_sw([2div_ctrl: b0 0x48(3)])=0 ant_ctrl1([2div_ctrl: b0 0x48(5)])=any (default setting) inv_ant_sw([2div_ctrl: b0 0x48(3)])=1 ant_ctrl1([2div_ctrl: b0 0x48(5)])=1 tx/rx state ant_sw trx_sw ant_sw trx_sw description idle l l h l idle state tx l h h h tx state l l h l when diversity disable or intial codition when diversity enable is set ([2div_ctrl: b0 0x48(0)]=0b1). rx h/l l l/h l if diversity enable is set, during searching (ant_sw=h) and (ant_sw=l) is switched alternatively. after diversity completion, fix to one of the condition. (2) antenna switch forced setting by [ant_ctrl: b0 0x4c] register, ant_sw pin output conditions can be set to fix. tx: by tx_ant_en([ant_ctrl: b0 0x4c(0)])=0b1, tx_ant([ant_ctrl: b0 0x4c(1)]) condition will be output. rx: by rx_ant_en([ant_ctrl: b0 0x4c(4)])=0b1, rx_ant([ant_ctrl: b0 0x4c(5)]) condition will be output. however, output is defined by [gpiio*_ctrl: b0 0x4e - 0x51] register , [gpiio*_ctrl:b0 0x4e - 0x51] registers setting has higer priority.
fedl7406-02 ML7406 63/104 antenna switching control signals can be also used as below. example 1) using one dpdt switch please set 2port_sw([2div_ctrl: b0 0x48(1)])=0b1. (note) altenate external pa control signal exists (goipn or ext_clk pin). (note) external circuits around lna_p pin, pa_out pin and antenna switch (dpdt#1) are omitted in this example. example 2) using 2 spdt switches please set 2port_sw([2div_ctrl: b0 0x48(1)])=0b0. (note) altenate external pa control signal exsits. (gpiox or ext_clk pin) (note) external circuits around lna_p pin, pa_outpin and antenna switch(spdt#2) are omitted in this example. dpdt#1 trx_sw output pin(gpiox) ant_sw output pin (gpiox) lna_p pin pa_out pin lsi spdt#1 spdt#2 lna_p pin pa_out pin lsi trx_sw output pin (gpiox) ant_sw output pin (gpiox)
fedl7406-02 ML7406 64/104 cca (clear channel assessment) function ML7406 supports cca function. cca function is to make a judment wheher the specified frequency channel is in-use or available. normal mode, continuous mode and idle detection mode are supported as following table. [cca mode setting] [cca_ctrl: b0 0x39] bit4 (cca_en) bit5 (cca_cpu_en) bit6 (cca_idle_en) normal mode 0b1 0b0 0b0 continuous mode 0b1 0b1 0b0 idle detection mode 0b1 0b0 0b1 (1) normal mode normal mode determines idle or busy. cca (normal mode) will be executed when rx_on is issued while cca_en(cca_ctrl: b0 0x39(4)])=0b1, cca_cpu_en(cca_ctrl: b0 0x39(5)])=0b0 and cca_idle_en (cca_ctrl: b0 0x39(6)])=0b0 are set. judgement of cca is determined by average ed value and cca threshold value defined by [cca_lvl: b0 0x37] register. if average ed value in [ed_rslt: b0 0x3a] register exceed s the cca threshold value, it is considered as ?busy?. and cca_rslt[1:0]([cca_ctrl: b0 0x39(1-0)]) =0b01 is set if average ed value is smaller than cca threshold value and maintains idle detection period which is defined by idle_wait[9:0] of the [idle_wait_l: b0 0x3b], [idle_wait_h: b0 0x3c] registers. it is considered as ?idle?. and cca_rslt[1:0]([cca_ctrl: b0 0x39(1-0)])=0b00 is set. for details operation of cca_idle_wait[9:0], please refer to ?idle detection for long time period? if busy or idle state is detected, cca completion interrupt (int[18] group3) is generated, cca_en bit is cleared to 0b0 automatically. upon clearing cca completion interrupt, cca_rslt[1:0]([cca_ctrl: b0 0x39(1-0)]) are reset to 0b00. therefore cca_rslt[1:0] should be read before clearing cca completion interrupt. if ed value exceeds the value defined by [cca_ignore_lvl: b0 0x36] register, and as lo ng as a given ed value is included in the averaging target of ed value calculation, idle judgement is not performed. in this case if average ed value exceeds cca threshold value, it is consider ed as ?busy? and cca is terminated. if average ed value is smaller than cca threshold valu, idle judgement is not determined. and cca_rslt[1:0] ([cca_ctrl: b0 0x39(1-0)]) indicates 0b11. cca operation continues until busy is determined or gievn ed value is out of averaging target and idle is determined. for details operation of ed value execeeding [cca_ignore_lvl: b0 0x36] register, please refer to ?idle determination exclusion under strong signal input?. timming from cca command issue to cca completion is in the formula below. [idle detection] cca execution timing = (ed value average times + idle_wait setting) * ad conversion time [busy detection] cca execution time = ed value average time * ad conversion time (note) 1. above formula does not consider idle judgement exclusion based on [cca_ignore_lvl: b0 0x36] register. for details, please refer to ?idle detection exclusion under strong signal input?. 2. ad conversion time can be slected by adc_clk_sel([adc_clk_set: b1 0x08(4)]). adc_clk_sel=0b0:17.7 s , 0b1:16 s(default)
fedl7406-02 ML7406 65/104 the following is timing chart for normal mode. [idle detection case] [busy result case] [condition] adc_ck_sel([adc_clk_set: b0 0x08(4)])=0b1 (2mhz) ed_avg[2:0] ([ed_ctrl: b0 0x41(2-0)])=0b011 (ed value 8 times average) idle_wait[9:0] ([idle_wait_l/h: b0 0x3c/3b(1-0)])=0b00_0000_0000 (idle detection 0 s) ed value (internal signal) cca_rslt[1:0] [cca_ctrl: b0 0x39(1-0)] int[18] (cca completion) [int_source_grp3: b0 0x0f(2)] cca_en [cca_ctrl: b0 0x39(4)] ed_value[7:0] [ed_rslt: b0 0x3a] ad conversion(16 s) ed value average period (16 sec8=128 s) 0b10 (cca on-going) ed1 ed3 ed5 ed2 ed6 ed7 ed ( 0-7 ) 0b00 (idle) *1 averaging cca execution period(min.128 s) < cca_lvl b0 0x37 idle_wait[9:0] should be set, for idle detection for longer period. ed0 ed value (internal signal) cca_rslt[1:0] [cca_ctrl: b0 0x39(1-0)] int[18] (cca completion) [int_source_grp3: b0 0x0f(2)] cca_en [cca_ctrl: b0 0x39(4)] ed_value[7:0] [ed_rslt: b0 0x3a] ad conversion (16 s) ed value average period (16 sec8=128 s) 0b10 (cca on-going) ed1 ed3 ed5 ed2 ed6 ed7 ed (0-7) 0b01 (busy) averaging > cca_lvl b0 0x37 idle_wait[9:0] should be set, for idle detection for longer period. ed0 *1 cca execution period (min.128 s) ed4 ed4
fedl7406-02 ML7406 66/104 (note) *1 during cca operation, if set bandwidth to be extended (default is not extended), enabling filter stabilization time by setting cca_mask_en([cca_mask_set: b2 0x7e(4)]) = 0b1. stabilization time should be 1 adc conversion time. if this register is enabled, input operation is suspended until filter become stable. (2) continuous mode continuous mode continues cca untill terminated by the host mcu. cca continuous mode will be executed when rx_on is issued while cca_en(cca_ctrl: b0 0x39(4)])=0b1, cca_cpu_en(cca_ctrl: b0 0x39(5)])=0b1 and cca_idle_en(cca_ctrl: b0 0x39(6)])=0b0 are set. like normal mode, cca judgement is determined by average ed value and cca threshold defined by [cca_lvl: b0 0x37] register. if average ed value in [ed_rslt: b0 0x3a] register exceed the cca threshold value, it is considered as ?busy?. and cca_rslt[1:0]([cca_ctrl: b0 0x39(1-0)]) = 0b01 is set. if average ed value is smaller than cca threshold value and maintains idle detection period which is defined by idle_wait[9:0] of the [idle_wait_l: b0 0x3b], [idle_wait_h: b0 0x3c] registers, it is considered as ?idle?. and cca_rslt[1:0]([cca_ctrl: b0 0x39(1-0)])=0b00 is set. for details operation of cca_idle_wait[9:0], please refer to ?idle detection for long time period?. if ed value exceeds the value defined by [cca_ignore_lvl: b0 0x36] register, as long as a given ed value is included in the averaging target of ed value calculation, idle judgement is not performed. in this case if average ed value exceed cca threshold level, it is considered as ?busy? and cca_rslt[1:0] ([cca_ctrl: b0 0x39(1-0)]) indicates 0b01. if average ed value is smaller than cca threshold level, idle judgement is not determined. and cca_rslt[1:0] ([cca_ctrl: b0 0x39(1-0)]) indicates 0b11. for details operation of ed value execeeding [cca_ignore_lvl: b0 0x36] register, please refer to ?idle determination exclusion under strong signal input?. continuous mode does not stop when busy or idle is detected. cca operation continues until 0b1 is set to cca_stop([cca_ctrl: b0 0x39(7)]). result is updated every time ed value is acquired. cca completion interrup (int[18] group3) will not be generated.
fedl7406-02 ML7406 67/104 the follwing is timing chart for continuous mode. [busy to idle transition, terminated with cca_stop] (note) *1 during cca operation, if set bandwidth to be extended (default is not extended), enabling filter stabilization time by setting cca_mask_en([cca_mask_set: b2 0x7e(4)]) = 0b1. stabilization time should be 1 adc conversion time. if this register is enabled, input operation is suspended until filter become stable. [condition] adc_ck_sel([adc_clk_set: b0 0x08(4)])=0b1 (2mhz) ed_avg[2:0] ([ed_ctrl: b0 0x41(2-0)])=0b011 (ed value 8 times average) idle_wait[9:0] ([idle_wait_l/h: b0 0x3c/3b(1-0)])=0b00_0000_0000 (idle detection period 0 s) ed (21-28) ed (43-50) ed value (internal signal) ad conversion (16 s) ed value average period (128 s) 0b10 (cca on-going) ed0 ed7 ed8 ed28 0b00 (idle) ed_value[7:0] [ed_rslt: b0 0x3a] invalid averaging > cca_lvl b0 0x37 ed (0-7) fedl7406-02 ML7406 68/104 (3) idle detection mode idle detection mode continues cca until idle detection. idle detection cca will be executed when rx_on is issued while cca_en(cca_ctrl: b0 0x39(4)])=0b1, cca_c pu_en(cca_ctrl: b0 0x39(5)])=0b0 and cca_idle_en (cca_ctrl: b0 0x39(6)])=0b1 are set. like normal mode, cca judgement is determined by average ed value and cca threshold defined by [cca_lvl: b0 0x37] register. if average ed value in [ed_rslt: b0 0x3a] re gister exceed the cca threshold value, it is considered as ?busy?. and cca_rslt[1:0]([cca_ctrl: b0 0x39(1-0)]) =0b01 is set. if average ed value is smaller than cca threshold value and maintains idle detection period which is defined by idle_wait[9:0] of the [idle_wait_l: b0 0x3b], [idle_wait_h: b0 0x3c] registers. it is considered as ?idle?. and cca_rslt[1:0]([cca_ctrl:b0 0x39(1-0)]) =0b00 is set. for details operation of cca_idle_wait[9:0], please refer to ?idle detection for longer period?. in idle detection mode, only when idle is detected, cca completion interrupt (int[18] group3 is generated. after idle detection, cca_en and cca_idle_en are reset to 0b0. upon clearing cca completion interrupt, cca_rslt[1:0]([cca_ctrl: b0 0x39(1-0)]) are reset to 0b00. cca_rslt[1:0] should be read before clearing cca completion interrupt. if ed value exceeds the value defined by [cca_ignore_lvl: b0 0x36] register, as long as a given ed value is included in the averaging target of ed value calculation, idle judgement is not performed. in this case, if average ed value is smaller than cca threshold level, idle determination is not performed and cca_rslt[1:0] ([cca_ctrl: b0 0x39(1-0)]) indicates 0b11. cca operation continues until given ed value is out of averaging target and idle is determined. for details of ed value exceeding [cca_ignor e_lvl: b0 0x36] register, please refer to ?idle determination exclusion under strong signal input?.
fedl7406-02 ML7406 69/104 the follwing is timing chart for idle detection. [upon busydetection, continue cca and idle detection case] (note) *1 during cca operation, if set bandwidth to be extended (default is not extended), enabling filter stabilization time by setting cca_mask_en([cca_mask_set: b2 0x7e(4)]) = 0b1. stabilization time should be 1 adc conversion time. if this register is enabled, input operation is suspended until filter become stable. [condition] adc_ck_sel([adc_clk_set: b0 0x08(4)])=0b1 (2mhz) ed_avg[2:0]([ed_ctrl: b0 0x41(2-0)])=0b011 (ed value 8 times average) idle_wait[9:0] ([idle_wait_l/h: b0 0x3c/3b(1-0)])=0b00_0000_0000 (idle detection period 0 s) ed (21-28) ed (22-29) ed value average period 0b10(cca on-going) ed0 ed7 ed8 ed28 0b00(idle) invalid averaging cca execution period(min.128 s+idle detection period) idle detection period ed (20-27) > cca_lvl b0 0x37 ed (0-7) ed (1-8) ed27 ed29 fedl7406-02 ML7406 70/104 (4) idle determination exclusi on under strong signal input if acquired ed value exceeds [cca_ignore_lvl: b0 0x36] register, idle dertermination is not performed as lon as a given ed value is included in the averaging target range. if average ed value including this strong ed value indicated in [ed_rslt: b0 0x39] rehgiser exceeds the cca threshold value defined by [cca_lvl: b0 0x37] register, it is considered as ?busy?. and cca_rslt[1:0]([cca_ctrl: b0 0x39(1-0)])=0b01 is set. if average ed value is smaller than cca threshold value, idle determination is not performed and cca_rslt[1:0]([cca_ctrl: b0 0x39(1-0)]) indicates 0b11 ?cca evaluation under going (ed value excluding cca judgement acquisition)?. cca will continue until idle or busy determination (in case of idle detection mode, idle is determined. in case of continuous mode, cca_stop([cca_ctrl: b0 0x39(7)]) is issued.) (note) cca completion interrupt (int[18] group3) is generated cca only when idle or busy is determined. therefore, if data whose ed value exceeds cca_ignore_lvl are input intermittently, neither idle or busy cane be determined and cca may continues. [ed value acquisition under extrem strong signal] ed value (analog) [cca_ignore_lvl: b0 0x36] ed value shift register (ed value 8 times average) [time 1] [time2] [time 3] [time 8] [time 9] averaging target includes ed value exceeding cca_ignore_lvl. in this case idle determination is not done. however, if averaging value exceeds cca_lvl, busy is determined. ed value, which includes cca_ignore_lvl, is out of averaging target. in this case, idle is determined. time ed value >cca_ignore_lvl
fedl7406-02 ML7406 71/104 the follwing is timing chart for cca determination exclusion under strong signal. [during idle_wait counting, detected extremly strong signal. after the given signal is out of averaging target, idle detection case] ed7 invalid ed (0-7) ed (1-8) ed (6-13) ed8 ed13 ed14 0x001 0x006 0b11(on-going) 0x000 ed (14-21) ed (7-14) ed value>cca_ignore_lvl detection and reset due to extreme strong signal detection, cca_rslt is not indicating idle. cca_rslt=0b11 do not generate interrupt ed15 ed (8-15) ed21 ed (22-29) ed22 ed (15-22) 0x007 ed29 0b00(idle) resume counting due to the extreme strong signal is out of averaging target. cca _rslt maintains until idle/busy detected. ed value>cca_ignore_lvl ed value cca _ lvl, t hen bus y detection. ) 0b10(on-going) ed value (internal signal) ed_value[7:0] [ed_rslt: b0 0x3a] cca_rslt[1:0] [cca_ctrl: b0 0x39(1-0)] int[18] (cca completion) [int_source_grp3: b0 0x0f(2)] cca_prog[9:0] [cca_prog_l/h:b0 0x3e/3d] ed value fedl7406-02 ML7406 72/104 (5) idle detection for longer time period when cca idle detection is performed for longer time period, idle_wait[ 9:0]([idle_wait_l/h:b0 0x3c/3b(1-0)] can be used. by setting idle_wait [9:0], averaging period longer than the period (for example, ad conversion16 s, 8 times average setting 128 s) can be possible. this function can be used for idle determination ? by counting times when average ed value becomes smaller than cca threshold defined by [cca_lvl: b0 0x37] register. when counting exceed idle_wait [9:0], idle determination is done. if average ed value exceeds cca threshold level, imemediately ?busy? is determined without wait for idle_wait [9:0] period. the following timing chart is idle detection setting idle_wait[9:0]. [ed value 8 timesv average idle detection case] (note) *1 during cca operation, if set bandwidth to be extended (default is not extended), enabling filter stabilization time by setting cca_mask_en([cca_mask_set: b2 0x7e(4)]) = 0b1. stabilization time should be 1 adc conversion time. if this register is enabled, input operation is suspended until filter become stable. [condition] cca normal mode adc_ck_sel([adc_clk_set: b0 0x08(4)])=0b1 (2mhz) ed_avg[2:0]([ed_ctrl: b0 0x41(2-0)])=0b011 (ed value 8 times average) idle_wait[9:0]([idle_wait_l/h: b0 0x3c/3b(1-0)])=0b00_0000_0011 (idle detection period 48 s) ed value (internal signal) cca_rslt[1:0] [cca_ctrl: b0 0x39(1-0)] int[18] (cca completion) [int_source_grp3: b0 0x0f(2)] cca_en [cca_ctrl: b0 0x39(4)] ed_value[7:0] [ed_rslt: b0 0x3a] ed value averaging period (128 s) 0b10 (detection on-going) ed1 ed8 ed2 ed7 ed9 ed10 ed11 ed (0 - 7) 0b00(idle) invalid averaging cca execution period(min.128 s+48 s=176 s) 0x001 0x000 0x002 0x003 idle detection period (48 s) < cca_lvl b0 0x37 idle_wait start (average ed value < cca_lvl) continue for ad conversion period 3 times (48 s), then idle detection done. ed (1 - 8) ed (2 - 9) ed (3 - 10 ad conversion (16 s) idle_wait[9:0] [idle_wait_l/h:b0 0x3c/3b] *1 ed0
fedl7406-02 ML7406 73/104 [ed value 1time idle detection case] (note) *1 during cca operation, if set bandwidth to be extended (default is not extended), enabling filter stabilization time by setting cca_mask_en([cca_mask_set: b2 0x7e(4)]) = 0b1. stabilization time should be 1 adc conversion time. if this register is enabled, input operation is suspended until filter become stable. ad conversion (16 s) 0b10(on-going) ed1 ed13 ed2 ed14 ed (0) 0b00(idle) invalid do not average cca execution period(min.16 s+224 s=240 s) 0x001 0x000 0x002 idle detection period(224 s) < cca_th ed (1) ed (2) ed3 0x00c 0x00d 0x00e ed (12) ed (13) ed (14) if idle_wait=0x000, idle detection here. ed0 ed value average period(16 s) (average ed value < cca_lvl) continue for ad conversion period 14 times (224 s ) , then idle detection done. ed value (internal signal) cca_rslt[1:0] [cca_ctrl: b0 0x39(1-0)] int[18] (cca completion) [int_source_grp3: b0 0x0f(2)] cca_en [cca_ctrl: b0 0x39(4)] ed_value[7:0] [ed_rslt: b0 0x3a] idle_wait[9:0] [idle_wait_l/h;b0 0x3c/3b] [condition] cca normal mode adc_ck_sel([adc_clk_set: b0 0x08(4)])=0b1 (2mhz) ed_avg[2:0]([ed_ctrl: b0 0x41(2-0)])=0b000 (ed value 1 time average) idle_wait[9:0]([idle_wait_l: b0 0x3c/h: b0 0x3c/3b(1-0)])=0b00_0000_1110 (idle detection period 224 s) *1
fedl7406-02 ML7406 74/104 (6) cca operation during diversity cca operation during antenna diversity during diversity, if cca command is issued, diversity terminated and cca starts. upon cca starting, antenna is fixed to reset value(*1), maintaining until next diversity search. however, if rx_ant_en([ant_ctrl:b0 0x4c(4)])=0b1 is set, antenna is specified by rx_ant([ant_ctrl: b0 0x4c(5)]). after cca completion, diversity will be executed agaim. *1 please refer to the ?antenna switching function?. acco rding to the default setting, ant_sw and trx_sw signals are set. (note) during cca operation, rx operation is performed at the same time, even if cca completion interrupt (int[18] group3) is not generated, syncword detection interrupt (int[13] gr oup2), rx fifo access error interrupt (int[12] group2), rx length error interrupt (int[11] group2), crc error interrupt (int[9] group2), rx completion interrupt (int[8] group2) or fifo-full interrupt (int[5] group1) can be generated. for details diversity function, please refer to the ?diversity function?. int[18] (cca completion) [ int _ source _ grp3: b0 0x0f ( 2 )] cca_en [cca_ctrl: b0 0x39(4)] ant_sw searching diversity cca searching diversity if rx_ant_en=0b1, switch to the antenna specified by rx_ant. if rx_ant_en=0b0. ant1 is default antenna. after cca completion, resume diversity search.
fedl7406-02 ML7406 75/104 during diversity , before rx_on state, cca is performed. if diversity on setting and cca operation setting is enabled before rx_on state, after rx_on state transition, diversity will not perform, but cca will start. after cca completion, diversity will be performed. int[18] (cca completion) [int_source_grp: b0 0x0f(2) ] cca_en [cca_ctrl: b0 0x39(4)] 2div_done [2div_rslt: b0 0x49(1-0)] ant_sw cca diversity search rx_on after cca completion, perform diversity. if rx_ant_en=0b1, switch to the antenna specified by rx_ant. if rx_ant_en=0b0. ant1 is default antenna.
fedl7406-02 ML7406 76/104 (7) cca threshold setting cca threshold value defined by [cca_lvl: b0 0x37] register, should be considered desired input leve (ed value), components variation, temperature fluctuation, loss at antenn a and matching circuits. input level and ed value are described in the follow table. ed value = 255 / 70 * (107 + input level[dbm]) however, if bpf setting modified and cca is executed, ed value become bigger than normal case. cca threshold can be set as below , taking this compensation and variations into account. cca threshold = 255 / 70 * (107 + input level[dbm] - variations ? other losses) + cca compensation item value variation (individual, temp.) 6db other loss antenna, matchich circuits loss cca compensation 12@100kbps, 15@200kbps, 0@other rate example) when input level threshold is set to -75dbm conditions:other losses 1db, 100kbps ccathreshold = 255 / 70 * (107 - 75 - 6 - 1) + 12 103 = 0x67 in order to validate whether cca threshold is optimised or not, cca should be executed and confirmimg level changing from idle to busy, every time input level is changed,
fedl7406-02 ML7406 77/104 othe r functions da ta rate setting function (1) data rate change setting ML7406 supports various tx/rx data rate setting defined by the following registers. tx: [tx_rate_h: b1 0x02] and [tx_rate_l: b1 0x03] registers rx: [rx_rate1_h: b1 0x04], [rx_rate1_l: b1 0x05] and [rx_rate2: b1 0x06] registers tx/rx data rate can be defined in the following formula. [tx] tx data rate [bps] = round (26mhz / 13/ tx_rate[11:0]) recommended values for each data rate are in the table below. registers value below are automatically set to [tx_rate_h],[ tx_rate_l] registers by setting tx_drate[3:0] ([drate_set: b0 0x06(3-0)]). tx data rate [kbps] [tx_rate_h][ tx_rate_l] register setting value data rate deviation [%] *1 1.2 1667d -0.02 2.4 833d 0.04 4.8 417d -0.08 9.6 208d 0.16 32.768 61d 0.06 50 40d 0.00 100 20d 0.00 200 10d 0.00 300 7d 3.17 400 5d 0.00 500 4d 0.00 *1 data rate deviation is assumption that frequency deviation of master clock(26mhz crystal oscillator or tcxo or spxo) is 0ppm. [rx] rx data rate [bps] = round (26mhz / {rx_rate1[11:0] [rx_rate2[6:0]}) recommended values for each data rate are in the table below. registers value below are automatically set to [rx_rate1_h][ rx_rate1_l] [rx_rate2] registers by setting rx_drate[3:0]( [drate_set:b0 0x06(7-4)] ). rx dta rate [kbps] [rx_rate1_h][rx_rate1_l] register setting value [rx_rate2] register setting 1.2 169d 0d 2.4 85d 0d 4.8 42d 0d 9.6 21d 0d 32.768 11d 72d 50 8d 65d 100 4d 65d 200 5d 26d 300 3d 29d 400 2d 32d 500 2d 26d (note) when low_rate_en([clk_set2:b0 0x03(0)])=0b1, [rx_rate1_h/l] and [rx_rate2] registers are not set automatically by setting rx_drate[3:0]. please calcurate appropriate values by replacing the 8.66mhz to 26mhz in the above formula and set them to each register.
fedl7406-02 ML7406 78/104 (2) other register setting associate with data rate change data rate can be cahnged by rx_drate[3:0] ([drate_s et(7-4)]) and tx_drate[3:0] ([drate_set(3-0)]), below registers may have to be changed. (note) 1. depending on data rate, the following chage may not be necessary. for details, please refer to each register description. 2. please change data rate setting in trx_off state. 3. after change of data rate setting, please execute rst1 [rst_set: b0 0x01(1)] (modem reset). registers parameters name address data rate drate_set b0 0x06 ch_space_h b1 0x23 channel space ch_space_l b1 0x24 gfsk_dev_h b1 0x30 frequency deviation(gfsk) gfsk_dev_l b1 0x31 fsk_dev0_h/gfil0 b1 0x32 fsk_dev0_l/gfil1 b1 0x33 fsk_dev1_h/gfil2 b1 0x34 fsk_dev1_l/gfil3 b1 0x35 fsk_dev2_h/gfil4 b1 0x36 fsk_dev2_l/gfil5 b1 0x37 fsk_dev3_h/gfil6 b1 0x38 fsk_dev3_l b1 0x39 fsk_dev4_h b1 0x3a frequencydeviation (fsk) fsk_dev4_l b1 0x3b fsk_tim_adj4 b1 0x3c fsk_tim_adj3 b1 0x3d fsk_tim_adj2 b1 0x3e fsk_tim_adj1 b1 0x3f frequency deviation time(fsk) fsk_tim_adj0 b1 0x40 if_freq_h b0 0x54 if frequency if_freq_l b0 0x55 if_freq_cca_h b0 0x56 if frequency during cca if_freq_cca_l b0 0x57 bpf coefficient bpf_co b0 0x5c bpf coefficient during cca bpf_co_cca b0 0x5d iff_adj_h b0 0x5e demodulator dc level adjustment iff_adj_l b0 0x5f iff_adj_cca_h b0 0x60 demodulator dc level adjustment during cca iff_adj_cca_l b0 0x61 demodulator adjustment1 demod_set1 b1 0x57 demodulator adjustment2 demod_set2 b1 0x58 demodulator adjustment3 demod_set3 b1 0x59 demodulator adjustment4 demod_set4 b1 0x5a demodulator adjustment5 demod_set5 b1 0x5b demodulator adjustment6 demod_set6 b1 0x5c demodulator adjustment7 demod_set7 b1 0x5d demodulator adjustment8 demod_set8 b1 0x5e demodulator adjustment9 demod_set9 b1 0x5f
fedl7406-02 ML7406 79/104 interrupt generation function ML7406 support interrupt generation function. when interrupt occurs, interrupt notification signal (sintn) become ?l? to signal interrupt to the host. interrupt elements are divided in to the 3 groups, [int_source_grp1: b0 0x0d], [int_source_grp2: b0 0x0e] and [int_source_grp3: b0 0x0f]. each interrupt element can be maskalable using [int_en_grp1: b0 0x10]. [int_en_grp2: b0 0x11] and [int_en_grp3: b0 0x12] registers. interrupt notification signal (sintn) can be output from gpio* or ext_clk. for output setting, please refer to [gpio1_ctrl: b0 0x4e], [gpio1_ctrl: b0 0x4f], [gpio2_ctrl: b0 0x50], [gpio3_ctrl: b0 0x51] and [extclk_ctrl: b0 0x52] registers. (note) if one of the unmask interrupt event occurs, sintn maintains low. (1) interrupt events table each interrupt event is described below table. register interrupt name description int[0] clock stabilizaion completion interrupt int[1] vco calibration completion interrupt/ fuse access completion interrupt int[2] pll unlock interrupt int[3] rf state transition completion interrupt int[4] fifo-empty interrupt int[5] fifo-full interrupt int[6] wake-up timer completion interrupt int_source_grp1 int[7] clock calibration completion interrupt int[8] rx completion interrupt int[9] crc error interrupt int[10] diversity search completion interrupt int[11] rx length error interrupt int[12] rx fifo access error interrupt int[13] syncword detection interrupt int[14] field checking interrupt int_source_grp2 int[15] sync error interrupt int[16] tx completion interrupt int[17] tx data request accept completion interrupt int[18] cca completion interrupt int[19] tx length error interrupt int[20] tx fifo access error interrupt int[21] reserved int[22] general purpose timer 1 interrupt int_source_grp3 int[23] general purpose timer 2 interrupt
fedl7406-02 ML7406 80/104 (2) interrupt generation timing in each interrupt generation, timing from reference point to interrupt generation (notification) are described in the following table. timeout procedure for interrupt notification waiting are also described below. (note) (1)the values are described in units of ?bit cycle? in the below tablee is the value at 100kbps. if using other data rate,, ple ase esitimate with appropriate ?bit cycle?. (2)below table uses the following format for tx/rx data. 10 byte 2 byte 1 byte 24 byte 2byte preamble syncword length user data crc (3)even if each interrupt notification is masked, in case of in terrupt occurence, interrupt elements are stored internally. therefore, as soon as interrupt notification is unmasked, interrupt will generate. interrupt notice reference point timing from reference point to interrupt generation or interrupt generation timing resetn release (upon power-up) 50 s int[0] clk stabilization completion sleep release (recovered from sleep) 50 s vco calibration completion vco calibration start 230 s int[1] fuse access completion resetn release 48 s int[2] pll unlock detection - (tx) during tx after pa enable. (rx) during rx enable after rx enable. tx_on command (idle) 210 s (rx) 192 s rx_on command (idle) 119 s (rx) 244 s trx_off command (tx) 147 s (rx) 4 s int[3] rf state transition completion force_trx_off command (tx) 147 s (rx) 4 s (tx) tx_on command (*1) nrz coding, empty trigger level is set to 0x02. rfwake-up(210 s)+35byte(preamble to 22 nd data byte) 8bit 10(bit cycle) =3010 s int[4] fifo-empty detection (rx) - by fifo read, remaining fifo data is under trigger level (tx) - by fifo write, fifo usage exceed trigger level int[5] fifo-full detection (rx) syncword detection nrz coding, full trigger level is set to 0x05. 6byte (length to 5 th data byte) 8bit 10 s(bit cycle) = 480 s int[6] wake-up timer completion sleep setting wake-up timer is completed. for details, please refer to ?wake-up timer? int[7] clock calibration completion calibration start calibration timer is completed. for details, please refer to ?low speed clock shift detection function?. int[8] rx completion syncword detection nrz coding 27byte (l-ength to crc) 8bi te 10(bit cycle)=2160 s int[9] crc error detection syncword detection (format a/b) each rx crc block calculation completion (format c) rx completion int[10] diversity search completion - syncword detection during diversity enable setting int[11] rx length error detection syncword detection 80 s (l-field 1byte) 160 s (l-field 2byte) int[12] rx fifo access error detection - (1)overflow occurs because fifo read is too slow. (2)underflow occurs because too many fifo data is read int[13] syncword detection - syncword detection int[14] field check completion - match or mismatch detected in field check (*1) before issuing tx_on, writing full length tx data to the tx_fifo.
fedl7406-02 ML7406 81/104 interrupt notice reference point timing from reference point to interrupt generation or interrupt generation timing int[15] sync error detection - during rx after syncword detection, out-of-sync detected. (when rxdio_ctrl[1:0] ([dio_set: b0 0x0c(7-6)]) =0b00 or 0b11.) int[16] tx completion tx_on command (*1) rf wake-up+[tx data+3](bit) =210 s+(39byte 8 +3) bit 10 s (bit cycle)=3360 s after int[17] tx data request accept completion - after full length data are written to the tx_fifo. int[18] cca completion cca execution start (1)normal mode (ed value calculation averaging times +idle_wait setting [idle_wait_h/l:b0 0x3b,3c]) ad conversion time (2) idle detection mode idle judgment case (ed value calculation averaging times +idle_wait setting [idle_wait_h/l:b0 0x3b,3c]) ad conversion time busy judgment case (ed value calculation averaging times) ad conversion time ad conversion time period can be changed by ad clock frequency ([adc_clk_sel:b1 0x08]) . ad clock frequency = 1.88mhz: 17.7 s, 2.0mhz: 16 s. for details, please refer to the ?cca (clear channel assessment) function?. int[19] tx length error detection - after set length value to [tx_pkt_len_h/l: b0 0x7a/7b] registers int[20] tx fifo access error detection - (1) when the next packet data is writren to the tx_fifo before transmitting previous packet data. (2) fifo overflow when writing (3) fifo underflow (no data) when transmitting int[21] reserved - - int[22] general purpose timer 1 completion timer start general purpose timer 1 completion general purpose timer clock cycle division setting [gt_clk_set: b0 0x33] general purpose timer interval setting [gt1_timer:b0 0x34] for details, please refer to the ?general purpose timer?. int[23] general purpose timer 2 completion timer start general purpose timer 2 completion general purpose timer clock cycle division setting [gt_clk_set: b0 0x33] general purpose timer interval setting [gt2_timer:b0 0x35] for details, please refer to the ?general purpose timer?. (*1) before issuing tx_on, writing full length tx data to the tx_fifo.
fedl7406-02 ML7406 82/104 (3) clearing interrupt conditions the following table shows the condition of clearing each intereupt. as a procedure to clear the interrup, it is recommended that the interrupt to be cleared after masking the interrupt. interrupt notification conditions for clearing interrupts int[0] clk stabilization completion after interrupt generated int[1] vco calibration completion /fuse access completion after interrupt generated int[2] pll unlock after interrupt generated int[3] rf state transition completion after interrupt generated int[4] fifo-empty after interrupt generated (must clear before next fifo-empty trigger timing) int[5] fifo-full after interrupt generated (must clear before next fifo-full trigger timing) int[6] wake-up timer completion after interrupt generated int[7] clock calibration completion after interrupt generated int[8] rx completion after interrupt generated int[9] crc error after interrupt generated int[10] diversity search completion after rx completion interrupt (int[8]), must clear together with rx completion interrupt. (note) during data reception, clearing is prohibited. int[11] rx length error after interrupt generated int[12] rx fifo access error after interrupt generated int[13] syncword detection after interrupt generated int[14] field checking after interrupt generated int[15] sync error after interrupt generated int[16/] tx completion after interrupt generated int[17] tx data request accept completion after interrupt generated int[18] cca completion after interrupt generated (note) clearing interrupt erase cca result as well. int[19] tx length error after interrupt generated int[20] tx fifo access error after interrupt generated int[21] reserved int[22] general purpose timer 1 after interrupt generated int[23] general purpose timer 2 after interrupt generated
fedl7406-02 ML7406 83/104 temperature measurement function ML7406 has temperature measurement function. this temperature information can be from a_mon pin (pin#23) as analog output or digital information using[temp: b1 0x09] register. analog or digital can be switched by [mon_ctrl: b0 0x4d] register. (note) please do not set temp_out( [mon_ctrl: b0 0x4d(4)]) and temp_adc_out( [mon_ctrl: b0 0x4d(5)]) at the same time. correct value reading may not be guaranteed. [analog output] ML7406 has current source circuits and its current flow thro ugh 75k ? connected to a_monpin (pin#23). from voltage information, temperature information can be obtained. current from current source circuits are 10 a at 25 ? c. the following formula can be used to calculate temperature from the current. itemp = (273+ temp) / (273+25) * 10 ( a) therefore, if 75k ? resister is connected, temperature can be calculated using the following formula. vamon = (273+ temp) / (275+25) * 10e-6 * 75000 if temperature is -40 ? c to 85 ? c, vamon will be 0.59v to 0.9v. the following formula can be used to calculate temperature from voltage . temp = vamon * 397.3 - 273 [digital output] digital temperature information is using 6 bit adc to convert from the above analog information. internally, 4samples information are added and indicates as 8bit information in [temp: b1 0x09] register. ignoring low 2 bits, upper 6bitare used for average temperature information. temperature information is updated every 16 s([adc_clk_set: b1 0x08] register. if 1.73mhzis selected, it is updated every 18.5 s.
fedl7406-02 ML7406 84/104 low speed clock shift detection function ML7406 has low speed shift detection function to compensate inaccurate clock generated by rc oscillator (external clock or internal rc oscillation circuits). by detecting frequency shift of the wake up timer, host can set wake-up timer parameters which taking frequency shift into consider ation. more accurate timer operation is possible by adjusting wake-up timer interval setting ([wut_interval_h/l: b0 0x2f/0x30]) or continuous operation timer interval ([wu_duration: b0 0x31]). setting register frequency shift detection clock frequency setting [clk_cal_set: b0 0x70] clock calibration time [clk_cal_time: b0 0x71] clock calibration result value [clk_cal_h: b0 0x72], [clk_cal_l: b0 0x73] this function is to measure low speed wake-up timer cycle by using accurate high speed internal clock and count result will be stored in [clk_cal_h/l: b0 0x72/0x73] registers. above setting and count numbers are as follows: high speed clock counter = {wakeup timer clock cycle[sleep/wu_set:b0 0x2d(2)] * clcok calibration time setting ([clk_cal_time:b0 0x71(5-0)]) / {master clock cycle (26mhz) / clock division setting value ([clk_cal_set: b0 0x70(7-4)])} clock calibration time is as follows: clock calibration time[s] = wakeup timer clock cycle * clock calibration time setting [example] assuming no division in the internal high speed clock, calibration time is set as 10 cycle. set 1,000 to wake-up interval timer: condition: wake-up timer clock frequency = 32.768khz detection clock division setting clk_cal_div[3:0][clk_cal_set: b0 0x70(7-4)] = 0b0000 clock calibration time setting [clk_cal_time] = 0x0a wake-up timer interval [wut_interval_h/l:b0 0x2f,30] = 0x03e8 theorical high speed clock count = (1/32.768khz) * 10 / (1/26mhz) = 7934(0x1efe) if getting [clk_cal_h/l:b0 0x72,73] = 0x1e17 (7703) counter difference = 7703 - 7934 = -231 frequency shift = 1/[{1 / 32.768khz + (-231) / 10 * 1/26mhz } - 1/32.768khz] = 0.983 khz then finding wake-up timer clock frequency accuracy is +3% higher. and the compensation vale (c) is calcurared as below: c= wake-up timer interval([wut_interval_h/l:b0 0x2f,30]) * frequecy shift / 32.768 = 1000 * 0.983khz / 32.768khz =30 therefore, setting [wut_interval_h/l:b0 0x2f,30] = 1000 +30 = 1030 = 0x0406 to achive more accurate inteval timinig. (note) if calibration time is too short or if high speed counter is divided into low speed clock, calibration may not be accurate.
fedl7406-02 ML7406 85/104 lsi adjustment items and adjustment method pa adjustment ML7406 has output circuits for 1mw and 20mw (10mw as well). output circuits can be selected by pa_mode[1:0] ([pa_mode: b0 0x67(5-4)]). pa_mode[1:0] output circuit 0b00 1mw 0b01 10mw 0b10 20mw 0b11 not allowed output power can be adjusted by the following 3 registers. coarse adjustment 1 pa_reg[3:0] ([pa_mode: b0 0x67(3-0)]) 16 resolutions coarse adjustment 2 pa_adj[3:0 ] ([pa_adj: b0 0x69(3-0)]) 16 resolutions fine adjustment pa_reg_fine_adj[4:0] ([pa_reg_fine_adj: b0 0x68(4-0)]) 32 resolutions coarse adjustment 1 : pa regulator voltage adjustment setting regulator voltage according to the desired output level. however, please set pa regulator voltage to less than [vdd_pa(pin#22) ? 0.3v]. pa_reg[3:0] [pa_mode:b0 0x67] pa regulator voltage[v] 0b0000 1.20 0b0001 1.32 0b0010 1.44 0b0011 1.56 0b0100 1.68 0b0101 1.80 0b0110 1.92 0b0111 2.04 0b1000 2.16 0b1001 2.28 0b1010 2.40 0b1011 2.52 0b1100 2.64 0b1101 2.76 0b1110 2.88 0b1111 3.00 coarse adjustment 2 : pa output gain adjustment controlling output power by adjusting pa gain. adjustment steps are 0.4db to 1.5db. [pa_adj: b0 0x69]=0x0f: output pa gain maximum. [pa_adj: b0 0x69]=0x00: output gain minimum. fine adjustment : pa regulator voltage fine adjustment fine tuning output power by adjusting pa regulator voltage. adjustment step is less than 0.2db. [pa_reg_fine_adj b0 0x68]=0x1f: maximum [pa_reg_fine_adj b0 0x68]=0x00: minimum (note) in order to achieve the most optimized result, matching circuits may vary depending on the output mode.
fedl7406-02 ML7406 86/104 pa output adjustment flow start end coarse adjustment 1: pa_mode setting and p a regulator adjustment [pa_mode: b0 0x67] coarse adjustment 2: pa output gain adjustment pa output gain adjustment [pa_adj: b0 0x69] fine adjustment: pa regulator fine adjustment [pa_reg_fine_adj: b0 0x68]
fedl7406-02 ML7406 87/104 i/q adjustment image rejection ratio can be adjusted by tuning iq si gnal balance. the adjustment procedure is as follows: 1. from sg, image frequency signal is input to ant pin. input signal source: no modulation.wave input frequency: channel frequency - (2if frequency) in case of 100kbps, if frequency = 720khz: please refer to the ?if frequency setting?. input level: -70dbm 2. issuing rx_on by [rf_status:b0 0x7b] register, by adjusting [iq_mag_adj: b0 0x6c] and [iq_phase_adj: b0 0x6d] registers, finding setting value so that ed value [ed_rslt: b0 0x3a] is minimum. i/q adjustment flow start power on sg output setting modulation: no modulation level : -70dbm frequency: ch frequency- 2x if frequency initialize setting * p lease refer to ?initialization table? rx_on issue [rf_status: b0 0x0b]] 1 end amplitude, phase confirm a mplitude/phase re-adjustment by changing range. [iq_mag_adj] 3lsb [iq_phase_adj] 6lsb so that ed value is minimum. phase adjustment by [iq_phase_adj: b0 0x6d] so that ed value is minimum. 1 phase value setting [iq_phase_adj: b0 0x6d] amplitude setting [iq_mag_adj: b0 0x6c] init. value 0x08 setting amplitude adjustment by [iq_mag_adj: b0 0x6c] so that ed value is minimum. amplitude setting [iq_mag_adj: b0 0x6c]
fedl7406-02 ML7406 88/104 vco adjustment in order to compensate vco operation margin, optimized ca pacitance compensation value should be set in each tx/rx operation and frequency. this capacitance compensa tion value can be acquired by vco calibration. by performing vco calibration when power-up or reset, acquired capacitance compensation values for upper limit and lower limit of operation frequency range (for both tx/rx), based on this value optimised capacitance value is applied during tx/rx operation. vco adjustment flow the following flow is the procedure for acquiring capacitance compensation value when power-up or reset. (note) vco calibration should be performed only during idle state . start end setting low limit frequency [vco_cal_min_i: b1 0x4d] [vco_cal_min_fh: b1 0x4e] [vco_cal_min_fm: b1 0x4f] [vco_cal_min_fl: b1 0x50] setting operation frequency range [vco_cal_max_n: b1 0x51] initialize setting vco calibration completion int. clear int[1] ( [int_source_grp1: b0 0x0d]) set vco_cal_start = 0b1 [vco_cal_start: b0 0x6f(0)] start calibration calibration operation completion wait vco calibration completion int? int[1] [int_source_grp1: b0 0x0d] no yes
fedl7406-02 ML7406 89/104 vco calibration is necessary every 0.6ms to 3.9ms. after completion, capacitance compensation values are stored in the following registers. capacitance compensation value at low limit frequency: [vcal_min: b1 0x52] capacitance compensation value at upper limit frequency: [vcal_max: b1 0x53] in actual operation, based on the 2 compensation values, the most optimized capacitance value for the frequency is calculated and applied. the calculated value is stored in [vco_cal: b0 0x6e]. by evaluation stage, if below values are stored in the mcu memory and uses these values upon reset or power-up, calibration operation can be omitted. registers to be saved in the mcu memory. [vco_cal_min_i: b1 0x4d] [vco_cal_min_fh: b1 0x4e] [vco_cal_min_fm: b1 0x4f] [vco_cal_min_fl: b1 0x50]] [vco_cal_max_n: b1 0x51] [vcal_min: b1 0x52] [vcal_max: b1 0x53] (note) 1. for low limit frequency, please use frequency at least 2.2mhz lower than operation frequency. 2. upper limit frequency should be selected so that operation frequency is in the frequency range. 3. in case of like a channel change, if the setting frequency is outside of calibration frequency range, calibration has to be performed again with proper frequency. 4. if pll unlock occures, pll unlock interrupt (int[02] group1) will geneate. the following shows the ML7406 opereation related with lsi state and pll_ld_en([pll_lock_detect:b1 0x0b(7)]) setting, after interrupt generation. pll lock detection control setting and ML7406 operation after interrupt generation lsi state check timig of pll unlock detection pll_ld_en=0b1 [pll_lock_detect:b1 0x0b(7)] pll_ld_en=0b0 [pll_lock_detect:b1 0x0b(7)] tx pa_on =?h? interrupt occurs and tx stops forcibly interrupt occurs and tx is continued rx rx enable =?h? interrupt occurs and rx is continued interrupt occurs and rx is continued vco low limit frequency setting vco low limit frequency can be set as described in the ?channel frequency setting?. i is set to [vco_cal_min_i:b0 0x4d] register, f is set to [vco_cal_min_fh:b0 0x4e], [vco_cal_min_fm:b0 0x4f], [vco_cal_min_fl:b0 0x50] registers in msb ? lsb order. example) if operation low limit frequency is 870mhz, setting value should be lower than 2.2mhz, then in following example, low limit frequency is set to 866mhz, master clock frequency is 26mhz. i = 866mhz/26mhz (integer part) = 33(0x21) f =(866mhz/26mhz-33)2 20 (integer part) = 12905550 (0xc4ec4e) setting values for each register is as follows: [vco_cal_min_i] = 0x21 [vco_cal_min_fh] = 0xc4 [vco_cal_min_fm] = 0xec [vco_cal_min_fl] = 0x4e
fedl7406-02 ML7406 90/104 vco upper limit frequency setting vco upper limit frequency is calculated as following formula, based on low limit frequency value and vco_cal_max_n[3:0] ([vco_cal_max_n: b1 0x51(3-0)]). vco calibration upper limit frequency = vco calibration low limit frequency (b1 0x4e-0x50) + f(b1 0x51) f is defined in the table below. vco_cal_max_n[3:0] f[mhz] 0b0000 0 0b0001 0.8125 0b0010 1.625 0b0011 3.25 0b0100 6.5 0b0101 13 0b0110 26 0b0111 52 0b1000 82.875 0b1001 104 other than above prohibited
fedl7406-02 ML7406 91/104 energy detection value (ed value) adjustment [ed value adjustment] ed value is calculated by rssi signal (analog signal) from rf part,. by performing the following adjustment, it is possible to correct the variation in lsis. the gain adjustment and related registers are described below. in order to cover wider input range, gain should be changed at given point. threshold for gain change points are set to [gain_ltom: b1 0x0c], [gain_mtoh: b1 0x0f]. [gain_adj_m: b1 0x10] and [gain_adj_l: b1 0x11] registers are used to addition values to maintain linearity when changing gain. rssi slope can be set to [rssi_mag_adj: b1 0x13] register so that ed value can be between 0x00(min) and 0xff(max). please set to these registers based on the ?initialization table?, do not change the setting for these registers for tuning. adjusting the input level variation for the same input level can be set to [rssi_adj: b0 0x66] register. it must compensate the slope before compensation defined by [rssi_mag_adj:b0 0x13] register. however, if positive value is set , ed value cannot be decreased down to 0x00 at low input signal level. if negative value is set, ed value cannot be increased up to 0xff. operation in the high gain range: rssi value>gain_htom, and move to middle gain. operation in the middle gain range: rssi value>gain_mtol, and move to low gain. gain_mtoh rssi value, and move to high gain. operation in the low gain range: gain_ltom rssivalue, and move to middle gain. low gain operation range rf input level gain_adj_m (b1 0x10) ed value gain_htom (b1 0x0e) high low rssi value(adc output) middle gain operation range gain_mtol (b1 0x0c) high gain operation range gain_ltom (b1 0x0d) gain_mtoh (b1 0x0f) gain_adj_l (b1 0x11) ed value rssi_adj (b0 0x66) rssi_mag_adj (b1 0x13)
fedl7406-02 ML7406 92/104 oscillation circuit adjustment in case of using a crystal oscillator (ML7406c), crystal oscillator frequency deviation can be tuned by adjusting load capacitance of xin pin (pin#5) and xout pin (pin #6). load capacitance can be adjusted by [osc_adj1: b0 0x62] and [osc_adj2: b0 0x63]. adjustable capacitance is as follows: [osc_adj1] coarse adjustment of load capacitance: 0.7pf/step (setting range: 0x00 to 0x0f) [osc_adj2] fine adjustment of load capacitance: 0.02pf/step (setteing range: 0x00 to 0x77) osc_adj oscillating frequency
fedl7406-02 ML7406 93/104 registers registers map addressing range for each register bank are 0x00-0x7f(128 bytes). grey colours in the table are unused bits or reserved bits . please use the initial setting value, as reserved bits may be used for functions not open to the customers. it may cause unexpected operation. each bank can be selected by [bank_sel] register (b0 0x00, b1 0x00, b2 0x00, b3 0x00), enabling each bank in bit7-4 (b*_acen) and specified bank number to bit3-0. if registers value is specified in the description, do not change.
fedl7406-02 ML7406 94/104 bank0 bit address [hex] register name description 7 6 5 4 3210 00 bank_sel register access bank selection 01 rst_set software reset setting 02 clk_set1 clock cofiguration 1 03 clk_set2 clock configuration 2 04 pkt_ctrl1 packet configuration 1 05 pkt_ctrl2 packet configuration 2 06 drate_set data rate setting 07 data_set1 tx/rx data configulation 1 08 data_set2 tx/rx data configulation 2 09 ch_set rf channel setting 0a rf_status_ctrl rfauto status transition control 0b rf_status rfstate setting and status indication 0c dio_set dio mode configuration 0d int_source_grp1 interrupt status for int0 to int7 0e int_source_grp2 interrupt status for int8 to int15 (rx) 0f int_source_grp3 interrupt statsu for int16 to int23 (tx) 10 int_en_grp1 interrupt mask for int0 to int7 11 int_en_grp2 interrupt mask for int8 to int15 12 int_en_grp3 interrupt mask for int16 to int23 13 crc_err_h crc error status (high byte) 14 crc_err_m crc error status (middle byte) 15 crc_err_l crc error status (low byte) 16 state_clr state clear control 17 txfifo_thrh tx fifo-full level setting 18 txfifo_thrl tx fifo-emptythreshold, fast_txenable thresold 19 rxfifo_thrh rx fifo-full thresold 1a rxfifo_thrl rx fifo-empty threshold 1b c__check_ctrl control field (c-field) detection setting 1c m__check_ctrl manufactute id field (m-field) detection setting 1d a__check_ctrl address field (a-field) detection setting 1e c_field_code1 c-field setting code #1 1f c_field_code2 c-field setting code #2 20 c_field_code3 c-field setting code #3 21 c_field_code4 c-field setting code #4 22 c_field_code5 c-field setting code #5 23 m_field_code1 m-field 1 st byte setting code #1 24 m_field_code2 m-field 1 st byte setting code #2 25 m_field_code3 m-field 2 nd byte setting code #1 26 m_field_code4 m-field 2 nd byte setting code #2 27 a_field_code1 a-field 1 st byte setting 28 a_field_code2 a-field 2 nd byte setting 29 a_field_code3 a-field 3 rd byte setting 2a a_field_code4 a-field 4 th byte setting 2b a_field_code5 a-field 5 th byte setting 2c a_field_code6 a-field 6 th byte setting 2d sleep/wu_set sleep execution and wake-up operation setting 2e wut_clk_set wake-up timer clock division setting 2f wut_interval_h wake-up timer interval setting (high byte) 30 wut_interval_l wake-up timer interval setting (low byte) 31 rx_duration continue operation timer (after wake-up) setting 32 gt_set general purpose timer configuration 33 gt_clk_set general purposetimer clock division setting 34 gt1_timer general purpose timer #1 setting 35 gt2_timer general purpose timer #2 setting
fedl7406-02 ML7406 95/104 bit address [hex] register name description 7 6 5 43210 36 cca_ignore_lvl ed threshold level setting for excluding cca judgement 37 cca_lvl cca threshold level setting 38 cca_abort timing setting for forced termination of cca operation 39 cca_ctrl cca control setting and result indication 3a ed_rslt ed value indication 3b idle_wait_h idle detection period setting during cca (high 2 bits) 3c idle_wait_l idle detection period setting during cca (low byte) 3d cca_prog_h idle detection elapsed time display (during cca high byte) 3e cca_prog_l idle detection elapsed time display during cca(low byte) i 3f-40 reserved 41 ed_ctrl ed detection control setting 42 txpr_len_h tx preamble length setting (high byte) 43 txpr_len_l tx preamblelength setting (low byte) 44 postamble_set postamble length and pattern setting 45 sync_condition1 rx preamble setting and ed control setting 46 sync_condition2 ed threshold setting during synchronization 47 sync_condition3 tolerance of bit error setting in rx preamble and syncword detection 48 2div_ctrl antenna diversity setting 49 2div_rslt antenna diversity result 4a ant1_ed ant1 ed value during antenna diversity 4b ant2_ed ant2 ed value during antenna diversity 4c ant_ctrl antenna control setting for tx, cca or rx 4d mon_ctrl monitor function setting 4e gpio0_ctrl gpio0 pin (pin#16) configuration setting 4f gpio1_ctrl gpio1 pin (pin#17) configuration setting 50 gpio2_ctrl gpio2 pin (pin#18) configuration setting 51 gpio3_ctrl gpio3 pin (pin#19) configuration setting 52 extclk_ctrl ext_clk pin (pin #10) control setting 53 spi/ext_pa_ctrl spi interface io configurattion /external pa control setting 54 if_freq_h if frequency setting (high byte) 55 if_freq_l if frequency setting (low byte) 56 if_freq_cca_h if frequency setting during cca operation (high byte) 57 if_freq_cca_l if frequency setting during cca operation (low byte) 58 bpf_adj_h bandpass filter capacitance adjustment (high 2 bits) 59 bpf_adj_l bandpass filter capacitance adjustment (low byte) 5a-5b reserved 5c bpf_co bpf coefficient 5d bpf_co_cca bpfcoefficient (cca) 5e iff_adj_h demodulator dc level adjustment (high 2 bits) 5f iff_adj_l demodulator dc level adjustment (low byte) 60 iff_adj_cca_h demodulator dc level adjustment during cca (high 7 bits) 61 iff_adj_cca_l demodulator dc level adjustment during cca (low byte) 62 osc_adj1 coarse adjustment of load capacito for oscillation circuits 63 osc_adj2 fine adjustment of load capaciatnce for oscillation circuits 64 osc_adj3 oscillation circuits bias adjustment 65 osc_adj4 oscillation circuits bias adjustment (high speed start-up) 66 rssi_adj rssi value adjustment 67 pa_mode pa mode setting/pa regulator coarse adjustment 68 pa_reg_fine_adj pa regulator fine adjustment 69 pa_adj pa gain adjustment 6a reserved 6b reserved 6c iq_mag_adj if i/q amplitude balance adjustment 6d iq_phase_adj if i/q phase balance adjustment
fedl7406-02 ML7406 96/104 bit address [hex] register name description 7 6 5 43210 6e vco_cal vco calibration setting or status indicarion 6f vco_cal_start vco calibration execution 70 clk_cal_set clock calibration setting 71 clk_cal_time clock calibration time setting 72 clk_cal_h clock calibration value readout (high byte) 73 clk_cal_l clock calibration value readout (low byte) 74 reserved 75 sleep_int_clr interrupt clear setting during sleep state 76 rf_test_mode tx test pattern setting 77 stm_state sate machine status and synchronization status indication 78 fifo_set fifo readout setting 79 rd_fifo_last rx fifo data usage status indication 7a tx_pkt_len_h tx packet length setting (high byte) 7b tx_pkt_len_l tx packet length setting (low byte) 7c wr_tx_fifo tx fifo 7d rx_pkt_len_h rx packet length indication (high byte) 7e rx_pkt_len_l rx packet length indication (low byte) 7f rd_fifo fifo read
fedl7406-02 ML7406 97/104 bank1 bit address [hex] register name description 7 6 5 4 3210 00 bank_sel bank selection 01 clk_out clk_out (gpion) output frequency setting 02 tx_rate_h tx data rate conversion setting (high 4 bits) 03 tx_rate_l tx data rate conversion setting (low byte) 04 rx_rate1_h rx data rate conversion setting1 (high 4 bits) 05 rx_rate1_l rx data rate conversion setting1 (low byte) 06 rx_rate2 rx data rate conversion setting2 07 reserved 08 adc_clk_set rssi adc clock frequency setting 09 temp temperature digital value indication 0a reserved 0b pll_lock_detect pll lock detection setting 0c gain_mtol threshold level setting for switching middle gain to low gain 0d gain_ltom threshold level setting for switching low gain to middle gain 0e gain_htom threshold level setting for switching high gain to middle gain 0f gain_mtoh threshold level setting for switching middle gain to high gain 10 rssi_adj_m rssi offset value setting during middle gain opoeration 11 rssi_adj_l rssi offset value setting during low gain operation 12 rssi_stable_time rssi stabilization wait time setting 13 rssi_mag_adj scale factor setting for ed value conversion 14 rssi_val rssi value indication 15 afc/gc_ctrl afccontrol/gain controlmode setting 16 crc_poly3 crc polynomial setting 3 17 crc_poly2 crc polynomial setting 2 18 crc_poly1 crc polynomial setting 1 19 crc_poly0 crc polynomial setting 0 1a reserved 1b txfreq_i tx frequency setting (i counter) 1c txfreq_fh tx frequency setting (f counter high 4bit) 1d txfreq_fm tx frequency setting (f counter middle byte) 1e txfreq_fl tx frequency setting (f counter low byte) 1f rxfreq_i rx frequency setting (i counter) 20 rxfreq_fh rx frequency setting (f counter high 4bit) 21 rxfreq_fm rx frequency setting (f counter middle byte) 22 rxfreq_fl rx frequency setting (f counter low byte) 23 ch_space_h channel space setting (high byte) 24 ch_space_l channel space setting (low byte) 25 sync_word_len syncword lenght setting 26 sync_word_en syncword enable setting 27 syncword1_set0 syncword #1 setting (bit24-31) 28 syncword1_set1 syncword #1 setting (bit16-23) 29 syncword1_set2 syncword #1 setting (bit8-15) 2a syncword1_set3 syncword #1 setting (bit0-7) 2b syncword2_set0 syncword #2 setting (bit24-31) 2c syncword2_set1 syncword #2 setting (bit16-23) 2d syncword2_set2 syncword #2 setting (bit8-15) 2e syncword2_set3 syncword #2 setting (bit0-7) 2f fsk_ctrl gfsk/fsk mudulation timing resolution setting 30 gfsk_dev_h gfsk frequency deviation setting (high 6 bits) 31 gfsk_dev_l gfsk frequency deviation setting (low byte) 32 fsk_dev0_h/gfil0 fsk 1 st frequency deviation setting (high 6 bits) / gaussian filter coefficient setting 0 33 fsk_dev0_l/gfil1 fsk 1 st frequency deviation setting (low byte) / gaussian filter coefficient setting 1 34 fsk_dev1_h/gfil2 fsk 2 nd frequency deviation setting (high 6 bits) / gaussian filter coefficient setting 2
fedl7406-02 ML7406 98/104 bank1(continue) bit address [hex] register name description 7 6 5 4 3210 35 fsk_dev1_l/gfil3 fsk 2 nd frequency deviation setting (low byte) / gaussian filter coefficient setting 3 36 fsk_dev2_h/gfil4 fsk 3 rd frequency deviation setting (high 6 bits) / gaussian filter coefficient setting 4 37 fsk_dev2_l/gfil5 fsk 3 rd frequency deviation setting (low byte) / gaussian filter coefficient setting 5 38 fsk_dev3_h/gfil6 fsk 4 th frequency deviation setting (high 6 bits) / gaussian filter coefficient setting 6 39 fsk_dev3_l fsk 4 th frequency deviation setting (low byte) 3a fsk_dev4_h fsk 5 th frequency deviation setting (high 6 bits) 3b fsk_dev4_l fsk 5 th frequency deviation setting (low byte) 3c fsk_tim_adj4 fsk 4 th frequency deviation hold timing seting 3d fsk_tim_adj3 fsk 3 rd frequency deviation hold timing seting 3e fsk_tim_adj2 fsk 2 nd frequency deviation hold timing seting 3f fsk_tim_adj1 fsk 1 st frequency deviation hold timing seting 40 fsk_tim_adj0 fsk no-deviation frequency (carrier frequency) hold timing seting 41-47 reserved 48 2div_mode antenna diversity mode setting 49 2div_search1 antenna diversity search time setting 1 4a 2div_search2 antenna diversity search time setting 2 4b 2div_fast_lvl ed threshold setting during antenna diversity fast mode 4c reserved 4d vco_cal_min_i vco calibration low limit frequency setting (i counter) 4e vco_cal_min_fh vco calibration low limit frequency setting (f counter high 4 bits) 4f vco_cal_min_fm vco calibration low limit frequency setting (f counter middle byte) 50 vco_cal_min_fl vco calibration low limit frequency setting (f counter low byte) 51 vco_cal_max_n vco_cal max frequency setting 52 vcal_min vco calibration low limit value indication and setting 53 vcal_max vco calibration upper limit value indication and setting 54-55 reserved 56 demod_set0 demodulator configulation 0 57 demod_set1 demodulator configulation 1 58 demod_set2 demodulator configulation 2 59 demod_set3 demodulator configulation 3 5a demod_set4 demodulator configulation 4 5b demod_set5 demodulator configulation 5 5c demod_set6 demodulator configulation 6 5d demod_set7 demodulator configulation 7 5e demod_set8 demodulator configulation 8 5f demod_set9 demodulator configulation 9 60 demod_set10 demodulator configulation 10 61 demod_set11 demodulator configulation 11 62 addr_chk_ctr_h address check counter indication (high 3 bit) 63 addr_chk_ctr_l address check counter indication (low byte) 64 wht_init_h whitening initializing state setting (high 1bit) 65 wht_init_l whiteningi initializing state setting (low 8bit) 66 wht_cfg whitening polynomial generation setting 67-7e reserved 7f id_code id code indication
fedl7406-02 ML7406 99/104 bank2 bit address [hex] register name description 7 6 5 4 3210 00 bank_sel bank selection 7e cca_mask_set filter stabilization setting during cca bank3 bit address [hex] register name description 7 6 5 4 3210 00 bank_sel bank selection 23 2mode_det 2 modes detection setting (mode-t and mode-c) (note) 1. other registers are closed register and access is limite d. accessible registers are written in the ?initialization table?.calibration operation, do not access bank1 registers.
fedl7406-02 ML7406 100/104 application circuits example the below diagram does not show decoupling capacitors for lsi power pins. 10uf decoupling capacitor should be pl aced to common 3.3v power pins . murata lqw15series inductors are recommended. figure.direct-tie exmaple figure. diversity exmaple
fedl7406-02 ML7406 101/104 package dimensions remarks for surface mount type package surface mount type package is very sensitive affected by heating from reflow process, humidity during storaging therefore, in case of reflow mouting process, please contact sales representa tive about product name, package name, number of pin, package code and required reflow process condition (reflow method, temperature, number of reflow process), storage condition.
fedl7406-02 ML7406 102/104 footprint pattern (recommendation) when laying out pc boards, it is important to design the foot pattern so as to give consideration to ease of mounting, bonding, positioning of parts, reliability, wiring, and elimination of slder bridges. the optimum design for the foot pattern varies with the materials of the substrate, the sort and thichness of used soldering paste, and the way of soldering. therefore when laying out the foot pattern on the pc boards, refer to this figure which mean t he mounting area that the package leads ar e allowable for soldering pc boards. p-wqfn32-0505-0.50-a63
fedl7406-02 ML7406 103/104 revision history page document no. release data before revision after revision revision description pedl7406-01 sep 14, 2012 - - preliminary version fjdl7406-01 june 12, 2013 - - initial release fjdl7406-02 july 9, 2013 - - 2nd revision (note) corrections in spelling , improvements in the description are not included in the revision history.
fedl7406-02 ML7406 104/104 notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage an d operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, s hould you incur any damage arising from any inaccuracy or misprint of such information, lapis semic onductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circui ts for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual propert y or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispu te arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical i njury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machiner y, nuclear-reactor controller, fuel-controller or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign ex change and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2012-2013 lapis semiconductor co., ltd.

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